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1 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog p reliminary p roduct s pecification features n com port decode n pc dma mailbox registers n host i/o mailbox n programmable fixed /romcs and /ramcs boundaries n 100-pin qfp and vqfp packages n 3.3 and 5.0-volt operating ranges n 0 c to +70 c temperature range notes: ? enhancements from the discrete s180 device. general description part cpu uart i/o speed (mhz) z80189 s180* 16550 24 33 Z8L189 s180* 16550 24 20 n fully static z180 ? mpu core* C on-chip 1 mbyte mmu C two enhanced uart channels (up to 512 kbps)? C two chain-linked dma channels? C x 2 clock multiplier C low-power consumption modes C two 16-bit timer/counters C clocked serial i/o C on-chip wait state generator (wsg) C on-chip interrupt controller C on-chip clock oscillator/generator n 16550 compatible mimic interface C 16 ma mimic output drive capability the z80189/Z8L189 are cost-effective modem controllers that address a new generation of data pumps having the hdlc formatting feature. data pumps of these types do not require an hdlc interface; therefore, the z80189 does not need the escc ? . the addition of the pc dma mailbox registers allow dma data transfer between the pc memory and the modem speaker/microphone codec. the z80189 is a smart peripheral controller chip for modem (in particu- lar v.34 applications), fax, voice messaging, and other communications applications. the z80189/Z8L189 consists of an enhanced z8s180 microprocessor, a 16550 mimic with increased mimic drive capability for direct connection to the ibm pc, xt, at bus, and 24 bits of parallel i/o. current pc modem soft- ware compatibility can be maintained with the z80189's ability to mimic the 16550 uart chip. the z80180 core is the intelligent controller between the data pump and 16550 mimic interface when used in internal applications. this intelligent controller performs the data compression and error correction on outgoing and incoming data. z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers the integration of com port decode circuitry to the z80189 allows the mimic to be selected for a specific com port address (pc com port address 1-4). com port decode circuitry is simplified by allowing the user to select the mimic com port addresses through software, in addition to eliminating the need for external circuitry required for com port decode logic. the pc dma and i/o mailbox interface can be used to provide communication paths between the pc host and the z80189. these new communication paths can be used for voice, dtad, or jumperless com port selection. notes: all signals with a preceding front slash, "/", are active low, e.g.: b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss
2 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog general description (continued) figure 1. z80189 block diagram pc isa bus enhanced s180 mpu baud rate generator 16550 mimic interface com decoder 8-bit parallel port c 8-bit parallel port b 8-bit parallel port a pc dma dma & i/o interface
3 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pin description figure 2. z80189/Z8L189 100-lead qfp pin identification ha3//rfsh hdrq1//busack ha4//wait ha0 /hddis/txa0 /hwr//cts0 /hrd//dcd0 hintr2 haen ha6 /nmi /reset /hdack1//busreq extal xtal phi /rd /wr /m1 /iocs2/e /mrd//mreq /iorq /halt vss /hcs/hc1 ha2 ha1/rxa0 z80189/Z8L189 100-pin qfp /int0 /int1/pc6 /int2/pc7 st a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a12 vss a14 a15 a16 a17 a18 vdd a19 d0 d1 d3 /ramcs vdd ha7/iei /iocs1/ieo vss ha8 pc4 pc0 pc1 /mwr/pc2 pc3 pc5 hd7/pa7 hd6/pa6 hd5/pa5 hd4/pa4 hd3/pa3 hd2/pa2 hd1/pa1 hd0/pa0 ev2 ev1 /romcs 100 1 95 5 10 15 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 d2 a10 d4 d5 d6 d7 pb0/txs pb1//cts0 pb2//dcd0 pb3/txa0 pb5/txa1 pb7/rxs//cts1 /hdack0/cka0//dreq0 vss ha9/cka1//tend0 hintr1/tout hc2/cks ha5//dreq1 vdd hdrq0//rts0 pb6/rxa1 pb4/rxa0 a13
4 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pin description (continued) figure 3. z80189/Z8L189 100-lead vqfp pin identification z80189/Z8L189 100-pin vqfp ev1 /romcs /ramcs hdrq0/rts0 vdd ha5//dreq1 hc2/cks hintr1/tout ha9/cka1//tend0 vss /hdack0/cka0//dreq0 pb7/rxs//cts1 pb6/rxa1 pb5/txa1 pb4/rxa0 pb3/txa0 pb2//dcd0 pb1//cts0 pb0/txs d7 d6 d5 d4 d3 d2 125 /hwr//cts0 /hrd//dcd0 hintr2 haen ha6 vdd ha7/iei /iocs/ieo vss ha8 pc4 pc0 pc1 /mwr/pc2 pc3 pc5 hd7/pa7 hd6/pa6 hd5/pa5 hd4/pa4 hd3/pa3 hd2/pa2 hd1/pa1 hd0/pa0 ev2 75 51 5 10 15 20 60 70 55 65 st a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 vss a13 a14 a15 a16 a17 a18 vdd a19 d0 d1 /hcs/hc1 /hddis/txa0 ha0 ha1/rxa0 ha2 /halt ha3//rfsh /iorq /mrd//mreq /iocs2/e /m1 /wr /rd phi vss xtal extal ha4//wait hdrq1//busack /hdack1//busreq /reset /nmi /int0 /int1/pc6 /int2/pc7 76 100 80 85 90 95 50 26 30 35 40 45
5 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog absolute maximum ratings symbol description min max units v cc supply voltage (*) C0.3 +7.0 v v in input voltage C0.3 v cc +0.3 v t opr operating temp. 0 70 c t stg storage temp. C55 +150 c stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the dc characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. all voltages are referenced to gnd (0v). positive current flows into the referenced pin (test load). available operating temperature range is: s=0 c to 70 c voltage supply range: +4.5v v cc +5.5v +3.0v v cc +3.6v all ac parameters assume a load capacitance of 50 pf. add 10 ns delay for each 50 pf increase in load up to a maximum of 150 pf for the data bus and 100 pf for address and control lines. ac timing measurements are referenced to 1.5 volts (except for clock, which is refer- enced to the 10% and 90% points). maximum capacitive load for phi is 125 pf. 1.4 v i oh 100 pf ol i = 2 ma = 250 m a figure 4. test load diagram notes: (*) voltage on all pins with respect to gnd.
6 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog dc characteristics z80189 (v cc = 5.0v 10% or v cc = 3.3v 10%, over specified temperature range unless otherwise noted.) symbol parameter min typ max unit condition v ih1 input h voltage v cc C0.6 v cc +0.3 v reset, extal, nmi, int0, int1, int2 v ih2 input h voltage 2.0 v cc +0.3 v except reset, extal, nmi, int0, int1, int2 v il1 input l voltage C0.3 0.6 v reset, extal, nmi, int0, int1, int2 v il2 input l voltage C0.3 0.8 v except reset, extal, nmi, int0, int1, int2 v oh1 output h voltage v all outputs 2.4 v i oh = C200 m a v oh2 output h phi v cc C0.6 v i oh = C200 m a v ol1 output l voltage 0.40 v i ol = 2.2 ma all outputs v ol2 output l phi 0.40 v i ol = 2.2 ma v oh all mimic outputs 2.4 v i oh = 16 ma,** v ol all mimic outputs 0.4 v i ol = 16 ma,** v oh all mimic outputs 2.4 v i oh =8 ma,v cc = 3.3 v** v ol all mimic outputs 0.4 v i ol =8 ma,v cc = 3.3 v** i il input leakage 10 m av in = 0 to v cc 5 current all inputs except xtal, extal i tl tri-state leakage current 10 m av in = 0 to v cc 5 i cc * power dissipation* 18 30 ma f = 20 mhz, 3.3v normal operation 80 120 ma f = 33 mhz, 5v i cc * power dissipation* 1.8 3.6 ma f = 20 mhz, 3.3v (system stop mode) 6 9 ma f = 33 mhz, 5v power dissipation 15 50 m a (standby mode) notes: * v ih min = v cc -1.0 v, v il max = 0.8 v (all output terminals are at no load). ** total loading current in or out of the z189 cannot exceed 150 ma from pins 41 to 70.
7 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 9 ? address opcode fetch cycle t1 t2 tw t3 t1 t2 tw t3 t1 i/o write cycle ? i/o read cycle ? /wait /mreq 6 1 3 2 4 5 19 20 19 20 7 8 12 11 7 11 29 /iorq 13 11 13 28 9 /rd /wr 22 26 and 26a 25 11 10 14 18 /m1 17 st data in data out /reset 15 16 15 16 27 21 23 24 62 63 68 67 62 63 67 68 figure 5. cpu timing (opcode fetch cycle, memory read/write cycle i/o read/write cycle) timing diagrams
8 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog figure 6. cpu timing (/int0 acknowledge cycle, refresh cycle, bus release mode halt mode, sleep mode, system stop mode) timing diagrams (continued) ? 32 31 33 30 15 16 39 40 41 42 34 35 35 34 37 36 38 38 43 [3] /inti /nmi /m1 [1] /iorq [1] /data in [1] /mreq [2] /rfsh [2] /busreq /busack address data /mreq, /rd, /wr, /iorq /halt 44 c7 /intscc notes: [1] during /int0 acknowledge cycle [2] during refresh cycle [3] output buffer is off at this point
9 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog figure 8. dma control signals 45 46 45 45 47 17 48 18 cpu or dma read/write cycle (only dma write cycle for /tendi) t1 t2 tw t3 t1 [3] [4] [2] [1] /dreqi (at level sense) /dreqi (at edge sence) /tendi st dma control signals [ 1] tdrqs and tdrqh are specified for the rising edge of clock followed by t3. [2] tdrqs and tdrqh are specified for the rising edge of clock. [3] dma cycle starts. [4] cpu cycle starts. figure 7. cpu timing 0 address /iroq t1 t2 tw t3 t1 13 25 9 /rd /wr t2 tw t3 i/o read cycle i/o write cycle 28 29 28 29 22 timing diagrams (continued)
10 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog timing diagrams (continued) t1 t2 tw tw t3 d7-d0 49 50 49 50 49 50 16 15 50 49 e bus release mode sleep mode system stop mode figure 9. e clock timing (memory read/write cycle i/o read/write cycle) figure 10. e clock timing
11 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog t2 tw t3 t1 t2 e (example: i/o read - opcode fetch) 54 49 52 50 53 51 53 49 50 54 e (i/o write) figure 11. e clock timing (minimum timing example of pwel and pweh) figure 12. timer output timing ? 55 tout timer data reg = 0000h timing diagrams (continued)
12 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog timing diagrams (continued) t3 t1 t2 ts ts t1 t2 32 31 33 43 44 /inti /nmi a18-a0 /mreq, /m1 /rd /halt slp instruction fetch next opcode fetch figure 13. sleep execution cycle
13 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog csi/o clock 57 57 59 58 59 58 61 60 60 61 11.5 tcyc 11 tcyc 11 tcyc 11.5 tcyc 16.5 tcyc 16.5 tcyc 56 56 transmit data (internal clock) transmit data (external clock) receive data (internal clock) receive data (external clock) figure 14. csi/o receive/transmit timing /mreq 71 /ramcs /romcs figure 15. /romcs and /ramcs timing timing diagrams (continued)
14 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog timing diagrams (continued) 7 11 t1 t2 tw t3 t1 address valid 0 address /mreq 13 24 8 9 22 /rd /wr figure 16. /mwr and /mrd timing extal vil1 65 66 vih1 vil1 vih1 figure 17. external clock rise time and fall time figure 18. input rise and fall time (except extal, /reset) 70 69
15 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ac characteristics (v cc = 5v 10% or v cc = 3.3v 10%, over specified temperature range unless otherwise noted 33 mhz characteristics apply only to 5v operation.) Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max unit notes 1 tcyc clock cycle time 50 2000 33 2000 ns [1] 2 tchw clock h pulse width 15 10 ns [1] 3 tclw clock l pulse width 15 10 ns [1] 4 tcf clock fall time 10 5 ns [1] 5 tcr clock rise time 10 5 ns [1] 6 tad /phi to address valid 15 15 ns 7 tas address valid to /mreq, /irq 5 5 ns 8 tmed1 /phi to /mreq delay 3 3 ns [3] 9 trdd1 /phi to /rd delay (ioc=1) 25 15 ns / phi to /rd delay (ioc=0) 25 15 ns 10 tm1d1 /phi to /m1 delay 35 15 ns 11 tah address hold time from (mreq, ioreq, rd, wr) 5 5 ns 12 tmed2 /phi to /mreq delay 25 15 ns 13 trdd2 /phi to /rd delay 25 15 ns 14 tm1d2 /phi to /m1 delay 40 15 ns 15 tdrs data read setup time 10 10 ns [3] 16 tdrh data read hold time 0 0 ns 17 tstd1 /phi to /st delay 30 15 ns 18 tstd2 /phi to /st delay 30 15 ns 19 tws wait setup time to /phi 15 10 ns [2] 20 twh wait hold time from /phi 10 5 ns 21 twdz /phi to data float display 35 20 ns 22 twrd1 /phi to /wr delay 25 15 ns 23 twdd /phi to write data delay time 25 15 ns 24 twds write data setup time to /wr 10 10 ns 25 twrd2 /phi to /wr delay 25 15 ns 26 twrp write pulse width (memory write cycle) 75 45 ns 26a twrp write pulse width (i/o write cycle) 130 70 ns 27 twdh write data hold time from /wr 10 5 ns 28 tiod /phi to /iorq delay (ioc=1) 25 15 ns /phi to /iorq delay (ioc=0) 25 15 ns 29 tiod2 /phi to /iorq delay 25 15 ns 30 tiod3 /m1 to /iorq delay 100 80 ns 31 tints /int setup time to /phi 20 15 ns 32 tinth /int hold time from /phi 10 10 ns 33 tnmiw nmi pulse width 35 25 ns 34 tbrs busreq setup time to /phi 10 10 ns 35 tbrh busreq hold time from /phi 10 10 ns 36 tbad1 /phi to /busack delay 25 15 ns 37 tbad2 /phi to /busack delay 25 15 ns 38 tbzd /phi to bus floating delay time 40 30 ns 39 tmewh mreq pulse width (high) 35 25 ns 40 tmewl mreq pulse width (low) 35 25 ns
16 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ac characteristics (continued) (v cc = 5v 10% or v cc = 3.3v 10%, over specified temperature range unless otherwise noted 33 mhz characteristics apply only to 5v operation.) Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max unit notes 41 trfd1 /phi to /rfsh delay 20 15 ns 42 trfd2 /phi to /rfsh delay 20 15 ns 43 thad1 /phi to /halt delay 15 15 ns 44 thad2 /phi to /halt delay 15 15 ns 45 tdrqs dreq setup time to /phi 20 15 ns 46 tdrqh dreq hold time from /phi 20 15 ns 47 tted1 /phi to /tend delay 25 15 ns 48 tted2 /phi to /tend delay 25 15 ns 49 ted1 /phi to /e delay 30 15 ns 50 ted2 /phi /or to /e delay 30 15 ns 51 pweh e pulse width (high) 25 20 ns 52 pwel e pulse width (low) 50 40 ns 53 ter enable rise time 10 10 ns 54 tef enable fall time 10 10 ns 55 ttod /phi to timer output delay 75 50 ns 56 tstdi csi/o transmit data delay (internal clock operation) 75 60 ns 57 tstde csi/o transmit data delay (external clock operation) 7.5 tcyc+75 7.5 tcyc+60 ns 58 tsrsi csi/o receive data setup time (internal clock operation) 1 1 phi cycles 59 tsrhi csi/o receive data hold time (internal clock operation) 1 1 phi cycles 60 tsrse csi/o receive data setup time (external clock operation) 1 1 phi cycles 61 tsrhe csi/o receive data hold time (external clock operation) 1 1 phi cycles 62 tres reset setup time to /phi 40 25 ns 63 treh reset hold time from /phi 25 15 ns 64 tosc oscillator stabilization time 20 20 ns 65 texr external clock rise time (extal) 10 5 ns 66 texf external clock fall time (extal) 10 5 ns 67 trr reset rise time 50 50 ms [2] 68 trf reset fall time 50 50 ms [2] 69 tir input rise time (except extal, reset) 50 50 ns [2] 70 tif input fall time (except extal, reset) 50 50 ns [2] 71 tdcs mreq valid to ramcs and romcs valid delay 5 5 ns [3] notes: [1] tcyc = tchw + tclw + tcf + tcr. [2] if the rise and fall times are greater than the specified maximums, other specifications will not be met. [3] sl1832 is test screened such that specifications 8, 15, and 71 are tested to 18 ns (tmeol + tors + trlcs = 18 ns).
17 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ac characteristics (continued) address 5 7 3 data in data out a7-a0 /iorq /rd data /wr data 6 2 2 4 9 8 1 read/write external bus master timing figure 19. read/write external bus master timing
18 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ac characteristics (continued) read/write external bus master timing table 1. external bus master timing Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max unit notes 1 tsa(wf)(rf) address to wr or rd fall time 20 20 ns 2 tsio(wf)(rf) iorq fall to wr or rd fall time 20 20 ns 3 th data hold time (from wr rise) 0 0 ns 4 tdrd(do) rd fall to data out delay 35 35 ns 5 tdrir(doz) rd, iorq rise to data float time 0 0 ns 6 tsdi(wrf) data in to wr fall setup time 20 20 ns 7 tsa(iorqf) address to iorq fall setup time 35 35 ns 8 tsa(rdf) address to rd fall setup time 35 35 ns 9 tsa(wrf) address to wr fall setup time 35 35 ns table 2. 16550 mimic timing Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max unit notes 1 tsar address setup to hrd fall time 30 30 ns 2 tscsr address setup to cs fall time 30 30 ns 3 tsaw address setup to hwr fall time 30 30 ns 4 tscsw hcs setup to hwr fall time 30 30 ns 5 tah address hold time 20 20 ns 6 tcsh hcs hold time 20 20 ns 7 tds data setup time 30 30 ns 8 tdh data hold time 30 30 ns 9 twc write cycle delay 2.5 2.5 phi cycles 10 trvd delay from hrd fall to data valid 125 125 ns 11 thz hrd rise to data float delay 100 100 ns 12 trc read cycle delay 125 125 ns 13 trdd hrd toggle to driver enable/disable 60 60 ns 14 tsint delay fromwr rbr reg. to assert hintr 2.0 2.0 phi cycles 15 trint delay from /hrd of rbr to deassert hintr 2.0 2.0 phi cycles 16 thr delay from /wr thr to reset hintr 2.5 2.5 phi cycles 17 tsti delay from mpu /rd of thr to assert hintr 2.0 2.0 phi cycles 18 tir delay from /rd to reset interrupt 75 75 ns
19 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog valid ha2, ha1, ha0 /hcs /hrd /hwr 1 2 3 4 5 6 figure 20. pc host /rd /wr timing table 3. pc host /rd /wr timing table z80l189-20 mhz z80189-33 mhz no symbol parameter min max min max units 1 tsar h address to/hrd fall setup 30 30 ns 2 tscsr /hcs to /hrd fall setup 30 30 ns 3 tsaw h address to /hwr fall setup 30 30 ns 4 tscsw /hcs to /hrd fall setup 30 30 ns 5 tah h address from /hrd /hwr hold 20 20 ns 6 tcsh /hcs from /hrd /hwr hold 20 20 ns 16550 mimic timing
20 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog figure 21. com port decode mode pc host /rd /wr timing table 4. com port decode mode pc host /rd /wr timing table Z8L189-20 mhz z80189-33 mhz no symbol parameter min max min max units 1 tsar h address to/hrd fall setup 30 30 ns 2 tscsr /hcs to /hrd fall setup 30 30 ns 3 tsaw h address to /hwr fall setup 30 30 ns 4 tscsw /hcs to /hrd fall setup 30 30 ns 5 tah h address from /hrd /hwr hold 20 20 ns 6 tcsh /hcs from /hrd /hwr hold 20 20 ns valid /ha3 - /ha9 haen /hrd /hwr 1 2 3 4 5 6 16550 mimic timing (continued)
21 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog valid hd7-hd0 /hrd 10 11 12 figure 23. data setup and hold, output delay, read cycle table 5. data setup and hold, output delay, read cycle table Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 7 tds data in to /hwr rise setup 30 30 ns 8 tdh data in from /hwr rise hold 30 30 ns 9 twc write cycle delay 2.5 2.5 phi cycles 10 trvd /hrd fall to data out valid delay 125 125 ns 11 thz /hrd rise to data out float delay 100 100 ns 12 trc read cycle delay 2.5 2.5 phi cycles figure 22. data setup and hold, output delay, write cycle valid hd7-hd0 /hwr 7 8 9 16550 mimic timing (continued)
22 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic timing (continued) /hrd /hddis 13 figure 24. driver enable timing table 6. driver enable timing table Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 13 trdd /hrd to driver enable/disable 60 60 ns figure 25. interrupt timing rcvr fifo 14 14 15 15 /wr (mpu) rbr hintr (trigger level) hintr (line status rdr /hrd lsr /hrd rbr
23 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic timing (continued) table 7. interrupt timing rcvr fifo table Z8L189-20 mhz z80189-33 mhz units no sym parameter min max min max 14 tsint delay from stop to set 2 2 phi cycles interrupt 15 trint delay from /hrd (rd rbr or rd lsr) 2 2 phi cycles to reset interrupt /rd (mpu) txfifo hintr thre /wr (host) thr /rd (host) 11r 17 16 18 figure 26. interrupt timing transmitter fifo
24 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic timing (continued) table 8. interrupt timing transmitter fifo table Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 16 thr delay from /wr 2.5 2.5 phi cycles (wr thr) to reset interrupt 17 tsti delay from stop to 2 2 phi cycles interrupt (thre) 18 tir delay from /rd to 2.5 2.5 phi cycles reset interrupt table 9. i/o port timing table Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 1 tspia(wr) data setup time to (port) wr fall 20 20 ns 2 tdwr(pia) data valid delay from wr rise 60 60 ns port (output) port output data 1 (out) port output data 2 (out) /wr port 1 2 1 2 1 2 figure 27. i/o port timing diagram
25 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc dma timing table 10. pc dma mailbox timing pd dma write: memory-read, i/o write dma bus cycle Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 1 tackwh /hdack active hold 144 144 ns /hwr inactive 2 twrs /hdack active to 301 301 ns /hwr active 3 twr /hwr active to 454 454 ns inactive 4 tvwr data valid to /hwr 133 133 ns inactive 5 tdwrh write data valid hold 25 25 ns from /hwr inactive table 11. pc dma mailbox timing pd dma read: i/o-read, memory-write dma bus cycle Z8L189-20 mhz z80189-33 mhz no sym parameter min max min max units 1 tackrh /hdack active hold 89 89 ns /hrd inactive 2 trds /hdack active to 62 62 ns /hrd active 3 trd /hrd active to 749 749 ns inactive 4 tvrd data valid from /hrd 215 215 ns active 5 tdrdh read data valid hold 0 0 ns from /hrd inactive 6 tdz data float from /hrd 50 50 ns inactive
26 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc dma timing diagrams figure 28. pc dma write: memory-read, i/o write dma bus cycle on pc at bus figure 29. pc dma read: i/o-read, memory-write dma bus cycle on pc at bus pc clock internal hdrqr hdrq /aen /hdack /hwr hd [0:7] valid 3 4 5 1 2 (1) (1) the hdrq will not fall inactive until it ses the falling edge of /hwr during the /hdack cycle. pc clock internal hdrqr hdrq /aen /hdack /hrd hd [0:7] valid 3 6 5 2 4 (1) 1 (1) the hdrq will not fall inactive until it sees the falling edge of /hrd during the /hdack cycle .
27 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pin description cpu signals a19-a0. address bus (input/output, active high, tri-state). a0-a19 form a 20-bit address bus. the address bus provides the address for memory data bus exchanges, up to 1 mbyte, and i/o data bus exchanges, up to 64k. the address bus enters a high impedance state during reset and external bus acknowledge cycles, as well as during sleep and halt states. this bus is an input when the external bus master is accessing the on-chip peripherals. d7-d0. data bus (bidirectional, active high, tri-state). d0- d7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from i/o and memory de- vices. the data bus enters the high impedance state during reset and external bus acknowledge cycles, as well as during sleep and halt states. /rd. read (input/output, active low, tri-state). /rd indi- cates that the cpu wants to read data from memory or an i/o device. the addressed i/o or memory device should use this signal to gate data onto the cpu data bus. /wr. write (output, active low, tri-state). /wr indicates that the cpu data bus holds valid data to be stored at the addressed i/o or memory location. /iorq. i/o request (input/output, active low, tri-state). /iorq indicates that the address bus contains a valid i/o address for an i/o read or i/o write operation. /iorq is also generated, along with /m1, during the acknowledgment of the /int0 input signal to indicate that an interrupt response vector can be placed onto the data bus. /m1. machine cycle 1 (input/output, active low). together with /mreq, /m1 indicates that the current cycle is the opcode fetch cycle of an instruction execution. together with /iorq, /m1 indicates that the current cycle is for an interrupt acknowledge. it is also used with the /halt and st signal to decode status of the cpu machine cycle. /mreq. memory request (input/output, active low, tri- state). /mreq indicates that the address bus holds a valid address for a memory read or memory write operation. /wait. (input, active low). /wait indicates to the mpu that the addressed memory or i/o devices are not ready for a data transfer. this input is used to induce additional clock cycles into the current machine cycle. the /wait input is sampled on the falling edge of t2 (and subsequent wait states). if the input is sampled low, then additional wait states are inserted until the /wait input is sampled high, at which time execution will continue. /halt. halt/sleep status (output, active low). this output is asserted after the cpu has executed either the halt or slp instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. it is also used with the /m1 and st signals to decode status of the cpu machine cycle. on exit of halt/sleep, the first instruc- tion fetch is delayed 16 clock cycles after the /halt pin goes high. /busack. bus acknowledge (output, active low tri-state). /busack indicates to the requesting device, the mpu address and data bus, and some control signals, have entered their high-impedance state. /busreq. bus request (input, active low). this input is used by external devices (such as dma controllers) to request access to the system bus. this request has a higher priority than /nmi and is always recognized at the end of the current machine cycle. this signal will stop the cpu from executing further instructions and places the address and data buses, and other control signals, into the high impedance state. /nmi. non-maskable interrupt (input, negative edge trig- gered). /nmi has a higher priority than /int and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. this signal forces cpu execution to continue at location 0066h. /int0. maskable interrupt request 0 (input, active low). this signal is generated by external i/o devices. the cpu will honor this request at the end of the current instruction cycle as long as the /nmi and /busreq signals are inactive. the cpu acknowledges this interrupt request with an interrupt acknowledge cycle. during this cycle, both the /m1 and /iorq signals will become active. /int1, /int2. maskable interrupt requests 1 and 2 (inputs, active low). this signal is generated by external i/o devices. the cpu will honor these requests at the end of the current instruction cycle as long as the /nmi, /busreq, and /int0 signals are inactive. the cpu will acknowledge these interrupt requests with an interrupt acknowledge cycle. unlike the acknowledgment for /int0, during this cycle neither the /m1 or /iorq signals will become active. these pins may be programmed to provide active low level, rising or falling edge interrupts. the level of the external /int1 and /int2 pins may be read through bits pc6 and pc7 of parallel port c.
28 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pin description (continued) /rfsh. refresh (output, active low, tri-state). together with /mreq,/rfsh indicates that the current cpu machine cycle and the contents of the address bus should be used for refresh of dynamic memories. the low order 8 bits of the address bus (a7-a0) contain the refresh address. /mrd. memory read (output, active low, tri-state). /mrd is active when both the internal /mreq and /rd signals are active. /mwr. memory write (output, active low, tri-state). /mwr is active when both the internal /mreq and /wr signals are active. z180 ? mpu uart and sio signals cka0, cka1. asynchronous clock 0 and 1 (bidirectional, active high). when in output mode, these pins are the transmit and receive clock outputs from the asci baud rate generators. when in input mode, these pins serve as the external clock inputs for the asci baud rate generators. cks. serial clock (bidirectional, active high). this line is the clock for the csio channel. /dcd0. data carrier detect 0 (input, active low). this is a programmable modem control signal for asci channel 0. /rts0. request to send 0 (output, active low, tri-state). this is a programmable modem control signal for asci channel 0. /cts0/cts1. clear to send 0 (input, active low). this line is a modem control signal for the asci channel 0 and 1. txa0. transmit data 0 (output, active high). this signal is the transmitted data from the asci channel 0. txs. clocked serial transmit data (output, active high). this line is the transmitted data from the csio channel. rxa0. receive data 0 (input, active high). this signal is the receive data to asci channel 0. rxs. clocked serial receive data (input, active high). this line is the receiver data for the csio channel. rxa1. received data asci channel 1. txa1. transmitted data asci channel 1. z180 ? mpu dma signals /tend0. transfer end 0 (outputs, active low). this output is asserted active during the last write cycle of a dma operation. it is used to indicate the end of the block transfer. /dreq0, /dreq1. dma request 0 and 1 (input, active low). /dreq is used to request a dma transfer from one of the on-chip dma channels. the dma channels monitor these inputs to determine when an external device is ready for a read or write operation. these inputs can be pro- grammed to be either level or edge sensed. z180 ? mpu timer signals t out . timer out (output, active high). t out is the pulse output from prt channel 1. this line is multiplexed with hintr1 of the 16550 mimic. 16550 mimic interface signals hd7-hd0. host data bus (input/output, tri-state). in z80189, the host data bus is used to communicate be- tween the 16550 mimic interface and the pc/xt/at. it is multiplexed with the pa7-pa0 of parallel port a. /hddis. host driver disable (output, active low). in z80189, this signal goes low whenever the pc/xt/at is reading data from the 16550 mimic interface. the /hddis pin should also go active low on each pc dma read cycle. ha2-ha0. host address (input). in z80189, these pins are the address inputs to the 16550 mimic interface. this address determines which register the pc/xt/at accesses. ha9-ha3, haen. host com port decode address (in- put). in z80189, these pins are multiplexed when com port decode is enabled (default). these pins are used to provide internal mimic enable when ha9-ha3 match the programmed mimic address field. haen is also used to access the pc dma mailbox registers. /hcs. host chip select (input, active low). in z80189, this input is used by the pc/xt/at to select the 16550 mimic interface for an access. the /hcs input is disabled when using the internal com port decoder. when setting the /hcs force bit in the cdr register, the /hcs output is asserted when ha3-ha9 is within the boundaries pro- grammed by bits 3-4 of the cdr register and /hrd or /hwr is asserted. /hcs is not asserted for pc dma mailbox accesses.
29 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog /hwr. host write (input, active low). in z80189, this input is used by the pc/xt/at to signal the 16550 mimic interface that a write operation is taking place. /hrd. host read (input, active low). in z80189, this input is used by the pc/xt/at to signal the 16550 mimic interface that a read operation is taking place. hintr1, hintr2. host interrupt (output, active high tri- state). in z80189, this output is used by the 16550 mimic interface to signal the pc/xt/at that an interrupt is pend- ing. in z80189 com port decode mode, the mimic inter- rupt request can be routed to either hintr1 or 2 depend- ing on the com port decode selected. the deselected hintr line will be forced to tri-state, while the selected hintr will follow what is programmed in the mimic master control register. hc1, hc2. host com select pin 1&2 (input). hc1 and hc2 are general-purpose inputs that can be used for com port selection. the status of these pins are read by use of the cdr register. the status of these pins can be used by firmware to select the appropriate com port address decode range. pc dma mailbox signals /hdack0, /hdack1. host dma acknowledge (input, active low). this input signal indicates to the z80189 that the pc dma controller has acknowledged the request and will begin data transfer. /hdack0 is multiplexed with /cka0 and /dreq0. /hdack1 is multiplexed with /busreq. hdrq0, hdrq1. host dma request (output, active high, tri-state). this output requests to the pc dma controller that the z80189 is ready for a dma data transfer. hdrq is multiplexed with /rts0. hdrq1 is multiplexed with /busack. parallel ports pa7-pa0. parallel port a (input/output). these lines can be configured as inputs or outputs on a bit-by-bit basis when the z80189 is operated in mode 0. pb7-pb0. parallel port b (input/output). these lines can be configured as inputs or outputs on a bit-by-bit basis when the port function is selected in the system configuration register. pc7-pc0. parallel port c (input/output). these lines can be configured as inputs or outputs on a bit by bit basis for bits pc5-pc0. bits pc7 and pc6 are input only and read the level of the external /int2 and /int1 pins. when /int2 and/or /int1 are in edge capture mode writing a 1 to the respective pc7, pc6 bit clears the interrupt capture latch. writing a 0 has no effect. emulation signals ev1, ev2. emulation select (input). these two pins determine the emulation mode the z180 mpu is in. they are as follows: ev2 ev1 mode 0 0 0 normal mode, on-chip z180 bus master. mode 1 0 1 emulation adapter mode mode 2 1 0 emulator probe mode mode 3 1 1 reserved system control signals st. status (output, active high). this signal is used with the m1 and /halt output to decode the status of the cpu machine cycle. /reset. reset signal (input, active low). /reset signal is used for initializing the mpu and other devices in the system. it must be kept in the active state for a period of at least 6 system clock cycles. iei. interrupt enable signal (input, active high). iei is used with the ieo to form a priority daisy chain when there is more than one interrupt driven peripheral. ie0. interrupt enable output signal (output, active high). in the daisy-chain interrupt control, ieo controls the interrupt of external peripherals. ieo is active when iei is 1 and the cpu is not servicing an interrupt from the on-chip peripherals. this pin is multiplexed with /iocs1. /iocs1. i/o chip select 1 (output, active low) is an auxiliary chip select that decodes a7, a6, /iorq, /m1 and effectively decodes the address space xx80 to xxbf for i/o transactions. a15 through a8 are not decoded so that the chip select is active in all pages of i/o address space. the /iocs1 function is the default on power on or reset condition and is changed by programming bit 2 in the interrupt edge/pin mux register.
30 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog system control signals (continued) /iocs2. i/o chip select 2 (output, active low) this pin is a secondary peripheral i/o chip select. this pin is active for i/o accesses between xxc0h to xxc7h or xxc8h to xxcfh (programmable by bit 1 of the iobrg register). /ramcs. ram chip select (output, active low). signal used to access ram based upon the address and the ramlbr and ramubr registers. /romcs. rom chip select (output, active low). signal used to access rom based upon the address and the rombr register. xtal. crystal (output, active high). crystal oscillator connection. this pin should be left open if an external clock is used instead of a crystal. the oscillator input is not a ttl level (reference dc characteristics). extal. external clock/crystal (input, active high). crystal oscillator connections. an external clock can be input to the z80189 on this pin when a crystal is not used. this input is schmitt-triggered. phi. system clock (output, active high). the output is used as a reference clock of the mpu and the external system. v cc . power supply. +5 volts v ss . power supply. 0 volts pin multiplexing to allow for com port decode and omission of escc core, pin multiplexing is changed with respect to the z182. escc ch.a pins will be replaced by com decode and asci ch.a pins as follows: rxda ? ha6 /trxca ? haen txda ? hintr2 dcdb ? /hrd//dcd0 /ctsb ? /hwr//cts0 note that asci channel 0 functions can be found in two places. these pins are ored with asci channel 0 func- tions that are multiplexed with port b (pins 35-39 qfp). /dcd0, /cts0, rxa0 inputs will come from 78, 79, 81 (respectively) when port b (0-4) is enabled. when mimic is disabled, /hddis pin doubles as txa0 output. note that /rts0 has also been changed to pin 50. when com decode bit is set (enabled during reset) the following pins become multiplexed as follows. /rfsh ? ha3 /wait ? ha4 /dreq1 ? ha5 /ha6 ? ha6 iei ? ha7 /ha8 ? ha8 cka1/tend0 ? ha9 /haen ? haen these pins are selected such that they are all high-z inputs at power up to prevent any problems with connecting address lines directly to pc bus. although, the com decode multiplexing is enabled on power-up, the com address decoding is disabled.
31 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog table 12. z80189 pin-out multiplexed pin descriptions primary, secondary pin functions pin # pin # default secondary vqfp qfp function function control 14 st 25 a0 36 a1 47 a2 58 a3 69 a4 710 a5 811 a6 912 a7 10 13 a8 11 14 a9 12 15 a10 13 16 a11 14 17 a12 15 18 v ss 16 19 a13 17 20 a14 18 21 a15 19 22 a16 20 23 a17 21 24 a18 22 25 v dd 23 26 a19 24 27 d0 25 28 d1 26 29 d2 27 30 d3 28 31 d4 29 32 d5 30 33 d6
32 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pin multiplexing (continued) table 12. z80189 pin-out (continued) multiplexed pin descriptions primary, secondary pin functions pin # pin # default secondary vqfp qfp function function control 31 34 d7 32 35 pb0 txs system config reg bit 5 33 36 pb1 /cts0 system config reg bit 5 34 37 pb2 /dcd0 system config reg bit 5 35 38 pb3 txa0 system config reg bit 5 36 39 pb4 rxa0 system config reg bit 5 37 40 pb5 txa1 system config reg bit 6 38 41 pb6 rxa1 system config reg bit 6 39 42 pb7 rxs//cts1 system config reg bit 6 40 43 /hdack0 cka0//dreq0 host dma enable reg bit 3 41 44 v ss 42 45 ha9 cka1//tendo com decode reg bit 0 43 46 hintr1 t out system config reg bit 2 44 47 hc2 cks com decode reg bit 0 45 48 ha5 /dreq1 (4) 46 49 v dd 47 50 hdrq0 /rtso (6) host dma enable reg bit 3 48 51 /ramcs 49 52 /romcs 50 53 ev1 51 54 ev2 52 55 hd0 pa0 sys config reg bit 1 53 56 hd1 pa1 sys config reg bit 1 54 57 hd2 pa2 sys config reg bit 1 55 58 hd3 pa3 sys config reg bit 1 56 59 hd4 pa4 sys config reg bit 1 57 60 hd5 pa5 sys config reg bit 1 58 61 hd6 pa6 sys config reg bit 1 59 62 hd7 pa7 sys config reg bit 1
33 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mpu functional description the z80189 includes a zilog z8s180 mpu (static z80180 mpu). this allows software code compatibility with exist- ing z80/z180 software code. the following is an overview of the major functional units of the z80189. architecture the z80189 combines a high performance cpu core with a variety of system and i/o resources useful in a broad range of applications. the cpu core consists of four functional blocks: n clock generator n bus state controller (dynamic memory refresh) n memory management unit (mmu) n central processing unit (cpu). the integrated i/o resources make up the remaining functional blocks: n direct memory access (dma controltwo channels) n asynchronous serial communications controller (asci, two channels) n programmable reload timers (prt, two channels) n clocked serial i/o n 16550 compatible mimic interface n com port decoder n pc dma mailbox registers n host i/o mailbox registers clock generator. this logic generates the system clock from either an external crystal or clock input. the external clock is divided by two, or one if programmed, and is provided to both internal and external devices. in addition, there is also a clock multiplier feature which doubles the internal clock frequency from that of the external clock input. bus state controller. this logic performs all of the status and bus control activity associated with both the cpu and some on-chip peripherals. this includes wait state timing, reset cycles, dram refresh, and dma bus exchanges. interrupt controller. this logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the cpu. to maintain compatibility with the z80 cpu, three different interrupt modes are supported. memory management unit. the mmu allows the user to map the memory used by the cpu (logically only 64 kbytes) into the 1 mbyte addressing range supported by the z80189. the organization of the mmu object code maintains compatibility with the z80 cpu while offering access to an extended memory space. this is accom- plished by using an effective common area-banked area scheme. central processing unit. the cpu is microcoded to provide a core that is object-code compatible with the z80 cpu. it also provides a superset of the z80 instruction set, including 8-bit multiply. this core has been modified to allow many of the instructions to execute in fewer clock cycles.
34 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog table 12. z80189 pin-out (continued) multiplexed pin descriptions primary, secondary pin functions pin # pin # default secondary vqfp qfp function function control 60 63 pc5 61 64 pc3 62 65 pc2 /mwr int edge/pin reg bit 3 63 66 pc1 64 67 pc0 65 68 pc4 66 69 ha8 67 70 v ss 68 71 /iocs1 ieo int edge/pin reg bit 2 69 72 ha7 iei (1) com decode reg bit 0 70 73 v dd 71 74 ha6 72 75 haen 73 76 hintr2 74 77 /hrd /dcd0 (2) 75 78 /hwr /cts0 (2) 76 79 /hddis txa0 sys conf reg bit 1 77 80 ha0 78 81 ha1 rxa0 (2) 79 82 ha2 80 83 /hcs hc1 (3) 81 84 /halt 82 85 ha3 /rfsh com decode reg bit 0 83 86 /iorq 84 87 /mreq /mrd int edge/pin reg bit 3 85 88 /iocs2 e i/o brg reg bit 2 86 89 /m1 87 90 /wr 88 91 /rd 89 92 phi 90 93 v ss 91 94 xtal 92 95 extal 93 96 ha4 /wait (5) com decode reg bit 0 94 97 hdrq1 /busack (6) host dma enable reg bit 2 95 98 /hdack1 /busreq (5) host dma enable reg bit 2 96 99 /reset 97 100 /nmi 98 1 /int0 99 2 /int1 pc6 100 3 /int2 pc7 all inputs feature an auto latch that assures that an uncon- nected input is seen as a logic high or logic low by both the z189 or any measurement device connected to the inputs. the auto latch will latch onto the previous state of input pin. notes: 1. iei pulled high internally when default function is active 2. pins also act as asci inputs only when port b is enabled 3. mimic access is disabled until the system configuration register is written. /hcs can be forced to output the result of com port decoder. 4. pin simultaneously acts as input for both default and secondary functions. 5. /wait is pulled high internally when default function is active. 6. upon power-up or reset, this pin is tri-state.
35 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog figure 30. z189 mpu block diagram timing & clock generator bus state control interrupt cpu dmacs (2) 16-bit programmable reload timers (2) clocked serial i/o port asynchronous sci (channel 0) asynchronous sci (channel 1) mmu data bus (8-bit) address bus (16-bit) /dreq1 /tend0 txa0 cka0/ /dreq0 rxa0 /rts0 /cts0 /dcd0 txa1 rxa1 ? tout txs rxs cks xtal extal /reset /rd /wr /m1 /mreq /iorq /halt /wait /busreq /busack /rfsh st e /nmi /int0 /int1 /int2 a19-a0 d7-d0 /cts1 /cka1
36 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mpu functional description (continued) dma controller dma controller. the dma controller provides high-speed transfers between memory and i/o devices. transfer op- erations supported are memory-to-memory, memory to or from i/o, and i/o-to-i/o. transfer modes supported are request, burst, and cycle steal. dma transfers can access the full 1 mbyte addressing range with a block length up to 64 kbytes, and can cross over the 64 kbytes boundaries. asynchronous serial communications interface (asci) the asci logic provides two individual full-duplex uarts. each channel includes a programmable baud rate gen- erator. the asci channels can also support a multiproces- sor communications format. for asci0, up to three modem control signals and one clock signal can be pinned out, while asci1 has a data-only interface and 1 clock signal. the receiver includes a 4-byte fifo, plus a shift register as shown in figure 31. reset dcd (asci0 with auto enables) and i/o stop mode conditions during reset and in i/o stop state, and for asci0 if /dcd0 is auto-enabled and is high, an asci is forced to the following conditions: n fifo empty n all error bits cleared (including those in the fifo) n receive enable cleared (cntla bit 6 = 0) n transmit enable cleared (cntla bit 5 = 0). if dcd is not auto-enabled, the /dcd pin has no effect on the fifos or enable bits. figure 31. asci receiver error latches 4x4 bit error fifo p f o b e e r k mp bit 4-byte data fifo error shift register rxa overrun error notes: pe = parity error fe = framing error or = overrun bk = break mp = multiprocessor bit sm1-0 sar18-16 source 11 000 ext (cka0/dreq) 11 001 asci0 rx 11 010 asci1 rx 11 011 ext (/dreq1) 11 100 * 11 101 * 11 110 * 11 111 * dm1-0 dar18-16 destination 11 000 ext (cka0//dreq0) 11 001 asci0 tx 11 010 asci1 tx 11 011 ext (/dreq1) 11 100 * 11 101 * 11 110 * 11 111 * * reserved do not use. table 13. sar18-16 and dar18-16 i/o device encoding
37 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog fifo and receiver operation the 4-byte receive fifo is used to buffer incoming data to reduce the incidence of overrun errors. when the re bit is set in the cntla register, the rxa pin is monitored for a low transition. one-half bit time after the low transition of the rxa pin, the asci samples rxa again. if it has gone back to high, the asci ignores the previous low transition and resumes looking for a new one, but if rxa is still low, it considers this a start bit and proceeds to clock in the data based upon the internal baud rate generator or the exter- nal cka pin. the number of data bits, parity, multiproces- sor and stop bits are selected by the mod2, mod1, mod0 and mp bits in the cntla and cntlb registers. after the data has been received, the appropriate mp, parity and one stop bit are checked. data and any errors are clocked into the fifos during the stop bit. interrupts, receive data register full flag, and dma requests will also go active during this time. error condition handling when the receiver places a data character in the receive fifo, it also places any associated error conditions in the error fifo. the outputs of the error fifo go to the set inputs of the software-accessible error latches. writing a 0 to cntla efr is the only way to clear these latches. in other words, when an error bit reaches the top of the fifo, it sets an error latch. if the fifo has more data and the software reads the next byte out of the fifo, the error latch remains set, until the software writes a 0 to the efr bit. the error bits are cumulative, so if additional errors are in the fifo, they will set any upset error latches as they reach the top. overrun error an overrun occurs if the receive fifo is full when the receiver has just assembled a byte in the shift register and is ready to transfer it to the fifo. if this occurs, the overrun error bit associated with the previous byte in the fifo is set. the latest data byte is not transferred from the shift register to the fifo in this case, and is lost. once an overrun occurs, the receiver does not place any further data in the fifo, until the last good byte received has come to the top of the fifo so that the overrun latch is set, and software then clears the overrun latch. assembly of bytes continues in the shift register, but this data is ignored until the byte with the overrun error reaches the top of the fifo and is cleared with a write of 0 to the efr bit. break detect a break is defined as a framing error with the data equal to all zeros. when a break occurs, the all-zero byte with its associated error bits are transferred to the fifo, if it is not full. if the fifo is full, an overrun is generated, but the break, framing error and data, are not transferred to the fifo. any time a break is detected, the receiver will not receive any more data until the rxa pin returns to a high state. if the channel is set in multiprocessor mode and the mpe bit of the cntla register is set to 1, then breaks, errors and data will be ignored unless the mp bit in the transmission is a 1. note: the two conditions listed above could cause a break condition to be missed if the fifo is full and the break occurs, or if the mp bit in the transmission is not a 1 with the conditions specified above. parity and framing errors parity and framing errors do not affect subsequent re- ceiver operation.
38 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mpu functional description (continued) baud rate generator the baud rate generator (brg) has two modes. the first is the same as in the z80180. the second is a 16-bit down counter that divides the processor clock by the value in a 16-bit time constant register, and is identical to the escc brg. this allows a common baud rate of up to 512 kbps to be selected. the brg can also be disabled in favor of an external clock on the cka pin. the receiver and transmitter will subsequently divide the output of the brg (or the signal from the cka pin) by 1, 16 or 64, under the control of the dr bit in the cntlb register, and the x1 bit in the asci extension control register. to compute baud rate, use the following formulas. if ss2,1,0 = 111, baud rate = f cka / clock mode else if brg mode baud rate = f phi / (2 * (tc+2) * clock mode) else baud rate = f phi / ((10 + 20*ps) * 2^ss * clock mode) where: brg mode is bit 3 of the asext register ps is bit 5 of the cntlb register tc is the 16-bit value in the asci time constant registers the tc value for a given baud rate is: tc = (f phi / (2 * baud rate * clock mode)) - 2 clock mode depends on bit 4 in asext and bit 3 in cntlb: x1 dr clock mode 00=16 01=64 10=1 1 1 = reserved, do not use. 2^ss depends on the three ls bits of the cntlb register: ss2 ss1 ss0 2^ss 000=1 001=2 010=4 011=8 100=16 101=32 110=64 1 1 1 = external clock from cka0 (see above). the requirement of having very close to the 50% duty cycle when the cka pin is used as an input, has been removed on the 189. minimum high and low times on cka0 are typical of most cmos devices. rdrf is set, and if enabled an rx interrupt or dma request is generated, when the receiver transfers a char- acter from the rx shift register to the rx fifo. the fifo merely provides margin against overruns. when theres more than one character in the fifo, and software or a dma channel reads a character, rdrf either remains set or is cleared and then immediately set again. similarly, if a receive interrupt service routine doesnt read all the char- acters in the rxfifo, rdrf and the interrupt request remain asserted. the rx dma request is disabled when any of the error flags pe or fe or ovrn are set, so that software can identify with which character the problem is associated. programmable reload timer (prt) this logic consists of two separate channels, each con- taining a 16-bit counter (timer) and count reload register. the time base for the counters is derived from the system clock (divided by 20) before reaching the counter. prt channel 1 provides an optional output to allow for wave- form generation. the t out output of prt1 is available on a multiplexed pin. clocked serial i/o (csio) the csi0 channel provides a half-duplex serial transmitter and receiver. this channel can be used for simple high- speed data connection to another microprocessor or microcomputer.
39 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog /m1 if the m1e bit of the operation mode control register is set to 1, the reti cycle occurs only once. the /m1 output is asserted low during the opcode fetch cycle, the /int0 acknowledge cycle, and the first machine cycle of the /nmi acknowledge. when m1e bit is rest to 0, the /m1 output is normally inactive an asserted low only during the refetch of the reti instruction sequence and during /into acknowledge cycle. z8s180 power-down modes the following is a detailed description of the enhance- ments to the z8s180 from the standard z80180 in the areas of standby, idle, and standby-quick recovery modes. add-on features there are five different power-down modes. sleep and system stop are inherited from the z80180. in sleep table 14. power down modes power-down cpu on-chip recovery recovery time modes core i/o osc. clkout source (minimum) sleep stop running running running reset, interrupts 1.5 clock i/o stop running stop running running by programming - system stop stop stop running running reset, interrupts 1.5 clock idle ? stop stop running stop reset, interrupts, busreq 8 +1.5 clock standby ? stop stop stop stop reset, interrupts, busreq 2 17 +1.5 clock (normal recovery) 2 6 +1.5 clock (quick recovery) mode, the cpu is in a stopped state while the on-chip i/os are still operating. in i/o stop mode, the on-chip i/os are in a stopped state while leaving the cpu running. in system stop mode, both the cpu and the on-chip i/os are in the stopped state to reduce current consumption. the z8s180 has added two additional power-down modes, standby and idle, to reduce current consumption even further. the differences in these power-down modes are summarized in table 14. notes: ? idle and standby modes are only offered in the z8s180. note that the minimum recovery time can be achieved if interrupt is used as the recovery source.
40 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog standby mode the z8s180 has been designed to save power. two low- power programmable power-down modes have been added; standby mode and idle mode. the standby/idle mode is selected by multiplexing d6 and d3 of the cpu control register (ccr, i/o address = 1fh). to enter standby mode: 1. set d6 and d3 to 1 and 0, respectively. 2. set the i/o stop bit (d5 of icr, i/o address = 3fh) to 1. 3. execute the sleep instruction. when the part is in standby mode, it behaves similar to the system stop mode which currently exists on the z80180, except that the standby mode stops the clock oscillator, internal clocks and reduces the power con- sumption to a minimum. since the clock oscillator has been stopped, a restart of the oscillator requires a period of time for stabilization. an 18- bit counter has been added in the z8s180 to allow for oscillator stabilization. when the part receives an external irq or busreq during standby mode, the oscillator is restarted and the timer counts down 2 17 counts before acknowledgment is sent to the interrupt source. the recovery source needs to remain asserted for duration of the 2 17 count, otherwise standby will be resumed. the following is a description of how the part exits standby for different interrupts and modes of operation. standby mode exit with /reset the /reset input needs to be asserted for a duration long enough for the crystal oscillator to stabilize and then exit from the standby mode. when /reset is de-asserted, it goes through the normal reset timing to start instruction execution at address (logical and physical) 0000h. the clocking is resumed within the z8s180 and at the system clock output after /reset is asserted when the crystal oscillator is restarted, but not yet stabilized. standby mode exit with bus request optionally, if the brext bit (d5 of cpu control register) is set to 1, the z8s180 exits standby mode when the /busreq input is asserted; the crystal oscillator is then restarted. an internal counter automatically provides time for the oscillator to stabilize, before the internal clocking and the system clock output of the z8s180 are resumed. the z8s180 relinquishes the system bus after the clocking is resumed by: - tri-state the address outputs a19 through a0. - tri-state the bus control outputs /mreq, /iorq, /rd and /wr. - asserting /busack. the z8s180 regains the system bus when /busreq is deactivated. the address outputs and the bus control outputs are then driven high; the standby mode is exited. if the brext bit of the cpu control register (ccr) is cleared, asserting the /busreq would not cause the z8s180 to exit standby mode. if standby mode is exited due to a reset or an external interrupt, the z8s180 remains relinquished from the sys- tem bus as long as /busreq is active.
41 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog standby mode exit with external interrupts standby mode can be exited by asserting input /nmi. the standby mode may also exit by asserting /int0, /int1 or /int2, depending on the conditions specified in the following paragraphs. /int0 wake-up requires assertion throughout duration of clock stabilization time (2 17 clocks). if exit conditions are met, the internal counter provides time for the crystal oscillator to stabilize, before the internal clocking and the system clock output within the z8s180 are resumed. 1. exit with non-maskable interrupts if /nmi is asserted, the cpu begins a normal nmi interrupt acknowledge sequence after clocking resumes. 2. exit with external maskable interrupts if an external maskable interrupt input is asserted, the cpu responds according to the status of the global interrupt enable flag ief1 (determined by the ite1 bit) and the settings of the corresponding interrupt enable bit in the interrupt/trap control register (itc: i/o address = 34h): a. if an interrupt source is disabled in the itc, asserting the corresponding interrupt input would not cause the z8s180 to exit standby mode. this is true regardless of the state of the global interrupt enable flag ief1. b. if the global interrupt flag ief1 is set to 1, and if an interrupt source is enabled in the itc, asserting the corresponding interrupt input causes the z8s180 to exit standby mode. the cpu performs an interrupt acknowledge sequence appropriate to the input be- ing asserted when clocking is resumed if: - the interrupt input follows the normal interrupt daisy chain protocol. - the interrupt source is active until the acknowledge cycle is completed. c. if the global interrupt flag ief1 is disabled, i.e., reset to 0, and if an interrupt source is enabled in the itc, asserting the corresponding interrupt input will still cause the z8s180 to exit standby mode. the cpu will proceed to fetch and execute instructions that follow the sleep instruction when clocking is re- sumed. if the external maskable interrupt input is not active when clocking resumes, the z8s180 will not exit standby mode. if the non-maskable interrupt (/nmi) is not active when clocking resumes, the z8s180 still exits the standby mode even if the interrupt sources go away before the timer times out, because /nmi is edge-triggered. the condition is latched internally once /nmi is asserted low. idle mode idle mode is another power-down mode offered by the z8s180. to enter idle mode: 1. set d6 and d3 to 0 and 1, respectively. 2. set the i/o stop bit (d5 of icr, i/o address = 3fh) to 1. 3. execute the sleep instruction. when the part is in idle mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the clkout, is stopped completely. idle mode is exited in a similar way as standby mode, i.e., reset, bus request or external interrupts, except that the 2 17 bit wake-up timer is bypassed; all control signals are asserted eight clock cycles after the exit conditions are gathered. standby-quick recovery mode standby-quick recovery mode is an option offered in standby mode to reduce the clock recovery time in standby mode from 2 17 clock cycles (6.5 ms at 20 mhz) to 2 6 clock cycles (3.2 m s at 20 mhz). this feature can only be used when providing an oscillator as clock source. to enter standby-quick recovery mode: 1. set d6 and d3 to 1 and 1, respectively. 2. set the i/o stop bit (d5 of icr, i/o address = 3fh) to 1. 3. execute the sleep instruction. when the part is in standby-quick recovery mode, the operation is identical to standby mode except when exit conditions are gathered, i.e., reset, bus request or external interrupts; the clock and other control signals are recovered sooner than the standby mode. note: if standby-quick recovery is enabled, the user must make sure stable oscillation is obtained within 64 clock cycles.
42 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z8s180 mpu register map notes: registers listed in boldface type represent new registers added to the z8s180. all register addresses not listed are reserved. register name i/o addr/access asci control register a ch 0 %0000/40/80 r/w asci control register a ch 1 %0001/41/81 r/w asci control register b ch 0 %0002/42/82 r/w asci control register b ch 1 %0003/43/83 r/w asci status register ch 0 %0004/44/84 r/w asci status register ch 1 %0005/45/85 r/w asci tx data register ch 0 %0006/46/86 r/w asci tx data register ch 1 %0007/47/87 r/w asci rx data register ch 0 %0008/48/88 r/w asci rx data register ch 1 %0009/49/89 r/w csio control register %000a/4a/8a r/w csio transmit/receive data reg. %000b/4b/8b r/w timer data register ch ol %000c/4c/8c r/w timer data register ch oh %000d/4d/8d r/w reload register ch ol %000e/4e/8e r/w reload register ch oh %000f/4f/8f r/w timer control register %0010/50/90 asci0 extension control reg. %0012/52/92 r/w asci1 extension control reg. %0013/53/93 r/w timer data register ch 1l %0014/54/94 r/w timer data register ch 1h %0015/55/95 r/w timer reload register ch 1l %0016/56/96 r/w timer reload register ch 1h %0017/57/97 r/w free running counter %0018/58/98 r/w asci0 time constant low %001a/5a/9a r/w asci0 time constant high %001b/5b/9b r/w asci1 time constant low %001c/5c/9c r/w asci1 time constant high %001d/5d/9d rw clock multiplier register %001e/5e/9e rw register name i/o addr/access cpu control register %001f/5f/9f r/w dma source addr register ch ol %0020/60/a0 r/w dma source addr register ch oh %0021/61/a1 r/w dma source addr register ch ob %0022/62/a2 r/w dma dest addr register ch ol %0023/63/a3 r/w dma dest addr register ch oh %0024/64/a4 r/w dma dest addr register ch ob %0025/65/a5 r/w dma byte count register ch ol %0026/66/a6 r/w dma byte count register ch oh %0027/67/a7 r/w dma memory addr register ch 1l %0028/68/a8 r/w dma memory addr register ch 1h %0029/69/a9 r/w dma memory addr register ch 1b %002a/6a/aa r/w dma i/o addr register ch 1l %002b/6b/ab r/w dma i/o addr register ch 1h %002c/6c/ac r/w dma i/o addr register ch 1b %002d/6d/ad r/w dma byte count register ch 1l %002e/6e/ae r/w dma byte count register ch 1h %002f/6f/af r/w dma status register %0030/70/b0 r/w dma mode register %0031/71/b1 r/w dma/wait control register %0032/72/b2 r/w il register %0033/73/b3 r/w int/trap control register %0034/74/b4 r/w refresh control register %0036/76/b6 r/w mmu common base register %0038/78/b8 r/w mmu bank base register %0039/79/b9 r/w mmu common/bank area register %003a/7a/ba r/w operation mode control register %003e/7e/be r/w i/o control register %003f/7f/bf r/w
43 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z8s180 mpu registers asci channels control registers figure 33. asci control register a (ch. 1) mpe re te /rts0 mpbr/ efr mod2 mod1 mod0 0 r/w 0 r/w 0 r/w 1 r/w x r/w 0 r/w 0 r/w 0 r/w bit upon reset r/w cntla0 mode selection addr 00h read - multiprocessor bit receive write - error flag reset request to send transmit enable receive enable multiprocessor enable 0 0 0 start + 7-bit data + 1 stop 0 0 1 start + 7-bit data + 2 stop 0 1 0 start + 7-bit data + parity + 1 stop 0 1 1 start + 7-bit data + parity + 2 stop 1 0 0 start + 8-bit data + 1 stop 1 0 1 start + 8-bit data + 2 stop 1 1 0 start + 8-bit data + parity + 1 stop 1 1 1 start + 8-bit data + parity + 2 stop figure 32. asci control register a (ch. 0) mpe re te cka1d mpbr/ efr mod2 mod1 mod0 0 r/w 0 r/w 0 r/w 1 r/w x r/w 0 r/w 0 r/w 0 r/w bit upon reset r/w cntla1 mode selection addr 01h read - multiprocessor bit receive write - error flag reset cka1 disable transmit enable receive enable multiprocessor enable 0 0 0 start + 7-bit data + 1 stop 0 0 1 start + 7-bit data + 2 stop 0 1 0 start + 7-bit data + parity + 1 stop 0 1 1 start + 7-bit data + parity + 2 stop 1 0 0 start + 8-bit data + 1 stop 1 0 1 start + 8-bit data + 2 stop 1 1 0 start + 8-bit data + parity + 1 stop 1 1 1 start + 8-bit data + parity + 2 stop
44 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z8s180 mpu registers (continued) asci channels control registers mpbt mp /cts/ ps ss2 ss1 ss0 invalid r/w 0 r/w ? r/w 0 r/w 0 r/w 1 r/w 1 r/w 1 r/w r/w cntlb0 clock source and speed select addr 02h bit upon reset dr pe0 divide ratio parity even or odd clear to send/prescale multiprocessor multiprocessor bit transmit ? /cts - depending on the condition of /cts pin. ps - cleared to 0. general ps = 0 ps = 1 divide ratio (divide ratio = 10) (divide ratio = 30) ss, 2, 1, 0 dr = 0 (x16) dr = 1 (x64) dr = 0 (x16) dr = 1 (x64) 000 ? ? 160 ? ? 640 ? ? 480 ? ? 1920 001 ? ? 320 ? ? 1280 ? ? 960 ? ? 3840 010 ? ? 640 ? ? 2560 ? ? 1920 ? ? 7680 011 ? ? 1280 ? ? 5120 ? ? 3840 ? ? 15360 100 ? ? 2560 ? ? 10240 ? ? 7680 ? ? 30720 101 ? ? 5120 ? ? 20480 ? ? 15360 ? ? 61440 110 ? ? 10240 ? ? 40960 ? ? 30720 ? ? 122880 111 external clock (frequency < ?) figure 34. asci control register b (ch. 0)
45 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog general ps = 0 ps = 1 divide ratio (divide ratio = 10) (divide ratio = 30) ss, 2, 1, 0 dr = 0 (x16) dr = 1 (x64) dr = 0 (x16) dr = 1 (x64) 000 ? ? 160 ? ? 640 ? ? 480 ? ? 1920 001 ? ? 320 ? ? 1280 ? ? 960 ? ? 3840 010 ? ? 640 ? ? 2560 ? ? 1920 ? ? 7680 011 ? ? 1280 ? ? 5120 ? ? 3840 ? ? 15360 100 ? ? 2560 ? ? 10240 ? ? 7680 ? ? 30720 101 ? ? 5120 ? ? 20480 ? ? 15360 ? ? 61440 110 ? ? 10240 ? ? 40960 ? ? 30720 ? ? 122880 111 external clock (frequency < ?) figure 35. asci control register b (ch. 1) mpbt mp /cts/ ps ss2 ss1 ss0 invalid r/w 0 r/w ? r/w 0 r/w 0 r/w 1 r/w 1 r/w 1 r/w r/w cntlb1 clock source and speed select addr 03h bit upon reset dr pe0 divide ratio parity even or odd read - status of /cts pin write - select ps multiprocessor multiprocessor bit transmit ? /cts - depending on the condition of /cts pin. ps - cleared to 0.
46 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog asci channels control registers (continued) figure 36. asci status register rdrf ovrn cts1e tdre tie 0 r 0 r 0 r 0 r 0 r/w r/w 1 r 0 r/w r/w s tat 1 transmit interrupt enable addr 05h bit upon reset rie fe transmit data register empty /cts1 enable receive interrupt enable framing error parity error pe 0 over run error receive data register full figure 37. asci status register (ch. 1) upon reset rdrf ovrn /dcd0 tdre tie 0 r 0 r 0 r 0 r 0 r/w r ?? r 0 r/w r/w stat0 transmit interrupt enable addr 04h bit rie fe transmit data register empty data carrier detect receive interrupt enable framing error parity error pe ? over run error receive data register full ? /dcd0 - depending on the condition of /dcd0 pin. tdre is reset to 0, when /ctso input is high. /cts0 pin = l: tdre = 1 /cts0 pin = h: tdre = 0 ??
47 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 76543210 transmit data tdr0 write only addr 06h 76543210 transmit data tdr1 write only addr 07h xxxxxxxx received data tsr0 read only addr 08h xxxxxxxx received data tsr1 read only addr 09h 00000000 7 65 4 321 0 reserved (program as 0.) dcd0 disable 0 = dcd0 auto-enables rx 1 = dcd0 advisory to sw cts0 disable 0 = cts0 auto-enables tx 1 = cts0 advisory to sw x1 bit clk ascio 0 = cka0 /16 or /64 1 = cka0 is bit clock brg0 mode 0 = as s180 1 = enable 16-bit brg counter break feature enable break detect (ro) send break 0 = normal xmit 1 = drive txa low new z8s180 register 00000000 7 65 4 321 0 break feature enable break detect (ro) send break 0 = normal xmit 1 = drive txa low brg1 mode 0 = as s180 1 = enable 16-bit brg counter x1 bit clk asci1 0 = cka1 /16 or /64 1 = cka1 is bit clock reserved (program as 0.) new z8s180 register figure 38. asci transmit data register (ch. 0) figure 39. asci transmit data register (ch. 1) figure 40. asci receive data register (ch. 0) figure 41. asci receive data register (ch. 1) figure 43. asci1 extension control register (i/o address 13) figure 42. asci0 extension control register (i/o address 12)
48 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog acsi time constant registers new z8s180 registers 76543210 76543210 76543210 76543210 register: asci0 time constant high address: 1bh register: asci1 time constant low address: 1ch register: asci1 time constant high address: 1dh register: asci0 time constant low address: 1ah clock multiplier register (z180 mpu address 1eh) bit 7. x2 clock multiplier mode. when this bit is set to 1, this allows the programmer to double the internal clock from that of the external clock. this feature will only operate effectively with frequencies of 10-16 mhz (20-33 mhz internal). when this bit is set to 0, the z189 device will operate in normal mode. upon powerup, this feature is disabled. bit 0-6 . reserved. maintains a logic 1 value when read. figure 44. clock multiplier register (z180 mpu address 1eh) new z8s180 register 01111111 reserved 7 65 4 321 0 x2 clock multiplier mode 0 = disable 1 = enable
49 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ef eie ss2 ss1 ss0 0 r 0 r/w 0 r/w 0 r/w 11 r/w 1 r/w 1 r/w r/w speed select addr 0ah bit upon reset - te transmit enable receive enable end interrupt enable end flag re cntr ss2, 1, 0 baud rate 000 ? ? 20 001 ? ? 40 010 ? ? 80 011 ? ? 100 figure 45. csi/o control register 76543210 read - received data write - transmit data trdr read/write addr 0bh figure 46. csi/o transmit/receive data register ss2, 1, 0 baud rate 100 ? ? 320 101 ? ? 640 110 ? ? 1280 111 external clock (frequency < ? ? 20)
50 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog timer data registers 76543210 tmdr0l read/write addr 0ch 76543210 tmdr1l read/write addr 14h 15 14 13 12 11 10 9 8 tmdr0h read/write addr 0dh when read, read data register l before reading data register h. 15 14 13 12 11 10 9 8 tmdr1h read/write addr 15h when read, read data register l before reading data register h. figure 47. timer 0 data register l figure 48. timer 1 data register l figure 49. timer 0 data register h timer reload registers 76543210 rldr0l read/write addr 0eh 76543210 rldr1l read/write addr 16h 15 14 13 12 11 10 9 8 rldr0h read/write addr 0fh 15 14 13 12 11 10 9 8 rldr1h read/write addr 17h figure 51. timer 0 reload register l figure 52. timer 1 reload register l figure 53. timer 0 reload register h figure 54. timer 1 reload register h figure 50. timer 1 data register h
51 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog timer control register tif1 tif0 toc0 tde1 tde0 0 r 0 r 0 r/w 0 r/w 0 r/w r/w 0 r/w 0 r/w r/w tcr timer down count enable 1,0 addr 10h bit upon reset toc1 tie0 timer output control 1,0 timer interrupt enable 1,0 timer interrupt flag 1,0 tie1 0 toc1,0 a15/tout 00 inhibited 01 toggle 10 0 11 1 figure 55. timer control register
52 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog free running counter 76 543 210 frc read only addr 18h figure 56. free running counter cpu control register the z8s180 has an additional register which allows the programmer to select options that directly affect the cpu performance as well as controlling the standby operat- ing mode of the chip. the cpu control register (ccr) allows the programmer to change the divide-by-two inter- nal clock to divide-by-one. in addition, applications where emi noise is a problem, the z8s180 can reduce the output drivers on selected groups of pins to 33% of normal pad driver capability which minimizes the emi noise generated by the part. figure 57. cpu control register d7 d6 d5 d4 d3 d2 d1 d0 cpu control register (ccr) addr 1fh lnio 0 = standard drive 1 = 33% drive or asci signals standby/idle enable 00 = no standby 01 = idle after sleep 10 = standby after sleep 11 = standbyafter sleep 64 cycle exit (quick recovery) 0 000 00 00 lnad/data 0 = standard drive 1 = 33% drive on a19-a0, d7-d0 lncpuctl 0 = standard drive 1 = 33% drive on cpu control signals lnphi 0 = standard drive 1 = 33% drive on ext.phi clock brext 0 = ignore busreq in standby/idle 1 = standby/idle exit on busreq clock divide 0 = xtal/2 1 = xtal/1
53 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog bit 7. clock divide select. bit 7 of the ccr allows the programmer to set the internal clock to divide the external clock by 2 if the bit is 0 and divide-by-one if the bit is 1. upon reset, this bit is set to 0 and the part is in divide-by-two mode. since the on-board oscillator is not guaranteed to operate above 20 mhz, an external source must be used to achieve the maximum 33 mhz operation of the part, i.e., an external clock at 66 mhz with 50% duty cycle. if an external oscillator is used in divide-by-one mode, the minimum pulse width requirement must be satisfied. bits 6 and 3. standby/idle enable. these two bits are used for enabling/disabling the idle and standby mode. setting d6, d3 to 0 and 1, respectively, enables the idle mode. in the idle mode, the clock oscillator is kept oscillating but the clock to the rest of the internal circuit, including the clkout, is stopped. the z8s180 enters idle mode after fetching the second opcode of a sleep instruction, if the i/o stop bit is set. setting d6, d3 to 1 and 0, respectively, enables the standby mode. in the standby mode, the clock oscil- lator is stopped completely. the z8s180 enters standby after fetching the second opcode of a sleep instruction, if the i/o stop bit is set. setting d6, d3 to 1 and 1, respectively, enables the standby-quick recovery mode. in this mode, its operations are identical to standby except that the clock recovery is reduced to 64 clock cycles after the exit conditions are gathered. similarly, in standby mode, the z8s180 enters standby after fetching the second opcode of a sleep instruction, if the i/o stop bit is set. bit 5. brext. this bit controls the ability of the z8s180 to honor a bus request during standby mode. if this bit is set to 1 and the part is in standby mode, a busreq is honored after the clock stabilization timer is timed out. bit 4. lnphi. this bit controls the drive capability on the phi clock output. if this bit is set to 1, the phi clock output is reduced to 33% of its drive capability. bit 2. lnio. this bit controls the drive capability of the external i/o pins of the z80189/z80l189. when this bit is set to 1, the output drive capability of the following pins is reduced to 33% of the original drive capability: - cks - txai - rxs/cts1 - cka0/dreq0 - txs - txa0 - ckai/tend0 - /rts0 bit 1. lncpuctl. this bit controls the drive capability of the cpu control pins. when this bit is set to 1, the output drive capability of the following pins is reduced to 33% of the original drive capability: - /busack - /mreq - test - /rd - /iorq - status - /wr - /rfsh - /m1 - /halt - e - /tend1 bit 0. lnad/data. this bit controls the drive capability of the address/data bus output drivers. if this bit is set to 1, the output drive capability of the address and data bus output is reduced to 33% of its original drive capability.
54 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog dma registers bcr0l read/write addr 26h bc7 bc0 bcr0h read/write addr 27h bc15 bc8 mar1l read/write addr 28h ma7 ma0 mar1h read/write addr 29h ma15 ma8 mar1b read/write addr 2ah ma16 ma19 - --- figure 58. dma 0 source address registers figure 60. dma 0 byte counter registers figure 61. dma 1 memory address registers figure 59. dma 0 destination address registers sar0l read/write addr 20h sa7 sa0 sar0h read/write addr 21h sa15 sa8 sar0b read/write addr 22h sa16 sa19 - --- bits 0-2 (3) are used for sar0b a19, x x x x a18, x x x x a17, 0 0 1 1 a16 0 1 0 1 dma transfer request ext (cka0//dreq0 asci0 rx asci1 rx ext (/dreq1) dar0l read/write addr 23h da7 da0 dar0h read/write addr 24h da15 da8 dar0b read/write addr 25h da16 da19 - --- bits 0-2 (3) are used for dar0b a19, x x x x a18, x x x x a17, 0 0 1 1 a16 0 1 0 1 dma transfer request ext (cka0//dreq0) asci0 tx asci1 tx ext (/dreq1)
55 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog bcr1l read/write addr 2eh bc7 bc0 bcr1h read/write addr 2fh bc15 bc8 iar1l read/write addr 2bh ia7 ia0 iar1h read/write addr 2ch ia15 ia8 figure 64. dma i/o address register ch. 1 figure 63. dma 1 byte count registers figure 62. dma i/o address registers d7 d6 d5 d4 d3 d2 d1 d0 alternating channels 0 = dma channels are independent 1 = toggle between dma channels for same device currently selected dma channel when bit 7 = 1 reserved, program as 0. 000 = dma1 ext tout/dreq 001 = dma1 asci0 010 = dma1 asci1 011 = dma1 ext cka0//dreq0 111 = reserved, do not program iar1b addr 2d new z8s180 register
56 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog dma register description bit 7. this bit should be set to 1 only when both dma channels are set to take their requests from the same device. if this bit is 1 (it resets to 0), the tend output of dma channel 0 sets a flip-flop, so that thereafter the devices request is visible to channel 1, but is not visible to channel 0. the internal tend signal of channel 1 clears the ff, so that thereafter, the devices request is visible to channel 0, but not visible to channel 1. if dma requests are from differing sources, dma channel 0 request will be forced onto dma channel 1 once tend output of dma channel 0 sets the flop-flop to alternate. bit 6. when both dma channels are programmed to take their requests from the same device, this bit (ff mentioned in the previous paragraph) controls which channel the devices request is presented to: 0 = dma 0, 1 = channel 1. when bit 7 is 1, this bit is automatically toggled by the channel end output of the channels, as described above. bits 5-3. reserved and should be programmed as 0. bits 2-0. with dim1, bit 1 of dcntl, these bits control which request is presented to dma channel 1, as follows: dim1 iar18-16 request routed to dma channel 1 0 000 /dreq1 0 001 asci0 tx 0 010 asci1 tx 0 011 ext cka0//dreq0 0 10x reserved, do not program. 0 1x0 reserved, do not program. 0 111 reserved, do not program 1 000 ext /dreq1 1 001 asci0 rx 1 010 asci1 rx 1 011 ext cka0//dreq0 1 10x reserved, do not program. 1 1x0 reserved, do not program. 1 111 reserved, do not program
57 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog de1 de0 die0 - dime 0 r/w 0 r/w 1 w 1 w 00 r/w 10 r r/w dma master enable addr 30h bit upon reset die1 /dwe0 dma interrupt enable 1, 0 dma enable bit write enable 1, 0 dma enable ch 1, 0 /dwe1 d s tat r/w figure 65. dma status register - - sm0 mmod - 110 r/w 0 r/w 00 r/w 01 r/w memory mode select addr 31h bit upon reset sm1 dm0 ch 0 source mode 1, 0 ch 0 destination mode 1, 0 dm1 dmode r/w r/w dm1, 0 00 01 10 11 destination m m m i/o address dar0+1 dar0-1 dar0 fixed dar0 fixed sm1, 0 00 01 10 11 source m m m i/o address sar0+1 sar0-1 sar0 fixed sar0 fixed 0 1 mode cycle steal mode burst mode mmod figure 66. dma mode registers
58 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog dma registers (continued) mwi1 mwi0 dms0 dim1 dim0 111 r/w 1 r/w 00 r/w 00 r/w dma ch 1 i/o memory mode select addr 32h bit upon reset dms1 iwi0 /dreqi select, i = 1, 0 i/0 wait insertion iwi1 dcntl r/w r/w r/w r/w r/w memory wait insertion dm1, 0 00 01 10 11 transfer mode m - i/o m - i/o i/o - m i/o - m address increment/decrement dmsi 1 0 sense edge sense level sense mwi1, 0 00 01 10 11 no. of wait states 0 1 2 3 iwi1, 0 00 01 10 11 no. of wait states 1 2 3 4 mar1+1 mar1-1 iar1 fixed iar1 fixed iar1 fixed iar1 fixed mar1+1 mar1-1 * note: * if using rom/ram chip select wait state generators, the z180 wait state generator should be set to 0. figure 67. dma/wait control register
59 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog system control registers il7 il6 - - - 000 r/w 00000 r/w interrupt vector low addr 33h bit upon reset - - il5 il r/w r/w refe refw - cyc1 cyc0 111 11100 r/w cycle select addr 36h bit upon reset - - refresh wait state refresh enable - rcr r/w r/w r/w r/w cyc1, 0 00 01 10 11 interval of refresh cycle 10 states 20 states 40 states 80 states trap ufo ite2 ite1 ite0 001 110 r/w 01 r/w /int enable 2, 1, 0 addr 34h bit upon reset - - - itc r/w r r/w r/w undefined fetch object trap figure 69. int/trap control register figure 70. refresh control register figure 68. interrupt vector low register
60 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog mmu registers cb7 cb6 cb2 cb1 cb0 000 r/w 0 r/w 00 r/w 00 r/w mmu common base register addr 38h bit upon reset cb3 cb4 cb5 cbr r/w r/w r/w r/w r/w bb7 bb6 bb2 bb1 bb0 000 r/w 0 r/w 00 r/w 00 r/w mmu bank base register addr 39h bit upon reset bb3 bb4 bb5 bbr r/w r/w r/w r/w r/w ca3 ca2 ba2 ba1 ba0 111 r/w 1 r/w 00 r/w 00 r/w mmu bank area register addr 3ah bit upon reset ba3 ca0 ca1 cbar r/w r/w r/w r/w r/w mmu common area register figure 72. mmu bank base register figure 71. mmu common base register figure 73. mmu common/bank area register
61 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog system control registers ioa7 ioa6 --- 000 11111 r/w i/o stop addr 3fh bit upon reset - - i/o address combination of 11 is reserved iostp icr r/w r/w r/w m1e /m1te --- 111 11 111 r/w i/o compatibility addr 3eh bit upon reset - - /m1 temporary enable /m1 enable /ioc omcr w r/w r/w notes: 1. this register should be programmed to 0x0xxxxxb (x = don't care) as a part of initialization. 2. if the m1e bit is set to 1, the processor does not fetch a reti instruction. figure 74. operation mode control register figure 75. i/o control register
62 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mimic register map register name mpu addr/access pcaddr/access mmc mimic master control reg. xxff r/w none ius/ip interrupt pending xxfe r/wb7 none ie interrupt enable xxfd r/w none ivec interrupt vector xxfc r/w none rtcr receive time constant xxfb r/w none ttcr transmit time constant xxfa r/w none dlm divisor latch (msbyte) xxf9 r only 01,dlab=1,r/w dll divisor latch (lsbyte) xxf8r only 00,dlab=1,r/w scr scratch register xxf7 r only 07 r/w msr modem status register xxf6 r/wb7-4 06 r only lsr line status register xxf5 r/wb6432 05 r only mcr modem control register xxf4 r only 04 r/w lcr line control register xxf3 r only 03 r/w ier interrupt enable register xxf1 r only 01,dlab=0 r/w rbr receiver buffer register xxf0 w only 00,dlab=0 r only thr transmitter holding reg. xxf0 r only 00,dlab=0 w only fscr fifo status and control xxec r/w7-4 none tttc tran. timeout time const. xxeb r/w none rttc rec. timeout time const. xxea r/w none iir interrupt identification none 02 r only fcr fifo control register xxe9 r only 02 w only z80189 pc dma mailbox brg,com_port, pia and misc registers register name mpu addr/access pcaddr/access pa data direction register xxedh r/w none pa data register xxeeh r/w none mimic modification register xxe9 w only none rom address boundary reg. xxe8 r/w none ramlbr ram lower boundary reg. xxe7 r/w none ramubr ram upper boundary reg. xxe6 r/w none pb data register xxe5 r/w none pb data direction register xxe4 r/w none brg high constant xxe1 r/w none brg low constant xxe0 r/w none interrupt edge/pin mux control xxdf r/w none pc data register xxde r/w none pc data direction register xxdd r/w none z80189 enhancements register xxd9 r/w none wsg chip select register xxd8 r/w none iobrg register xxd6 r/w none com decode register xxd7 r/w none system configuration register xxef r/w none
63 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mailbox register map register name mpu addr/access pc addr/access host i/o status register %xxd5 w bit 1/r prog + 10b r (2) host output register 1 %xxd4 r prog + 01b w (2) host input register 1 %xxd4 w prog + 01b r (2) host output register 0 %xxd3 r prog + 00b w (2) host dma mailbox cntrl reg %xxd2 r/w none host dma transmit register 1 %xxd1 r dma1 w (3) host dma receive register 1 %xxd1 w dma1 r host dma transmit register 0 %xxd0 r (1) dma0 w host dma receive register 0 %xxd0 w dma0 r 1. this register is defaulted to 91h to indicate revision code. (z189 revision #1 - z80189aa) 2. the pc host addresses are ha9:2 are programmable by writing to padata. 3. the hdmat1 can be used as an extra host output mailbox register. if the host dma mailbox 1 function is disabled (bit 1 of hmc register is zero), a host write in the programmed mailbox range with ha1, 0=1,1 will cause the host data to be latched into the hdmat1 register. note: all register addresses not listed are reserved.
64 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic interface the z80189 has a 16550 mimic interface that allows it to mimic the 16550 device. it has all the interface pins necessary to connect up to the pc/xt/at bus without any extra circuitry. it contains the complete register set of the 16550 part with the same interrupt structure. the data path allows parallel transfer of data to and from the register set by the internal z80180 of the z80189. there is no shift register associated with the mimic of the 16550 uart. this interface saves the application from doing a serial transfer before performing data compression or error correction on the data. control of the register set is maintained by six priority encoded interrupts to the z80189. when the pc/xt/at writes to thr, mcr, lcr, dll, dlm, fcr or reads the rbr, an interrupt to the z80189 is generated. each inter- rupt can be individually masked off or all interrupts can be disabled by writing a single bit. both mode 0, mode 1 and mode 2 interrupts are supported by the 16550 mimic interface. two 8-bit timers are also available to control the data transfer rate of the 16550 mimic interface. their input is tied to the brg clock so a down count of 24 bits is possible. an additional two 8-bit timers are available for program- ming the fifo time-out feature (4 character time emula- tion) for both receiver and transmitter fifos. the 16550 mimic interface supports the pc/xt/at inter- rupt structure as well as an additional mode that allows for a wired and interrupt structure. all registers of the 16550 mimic interface are accessible in any page of i/o space since only the lowest 8 address lines are decoded. com port decode functionality is integrated into the z189. this allows the mimic to be selected for a specific com port address (pc com port address 1-4). previously for the z80182, the com port address selected for the mimic was implemented through external com port decode circuitry. the com port decode circuitry in the z80189 simplifies this process by allowing the user to select the mimic com port addresses through software, as well as reducing the system board level costs by saving board space and external circuitry. see figure 76 for a block diagram of the 16550 mimic interface. figure 76. 16550 mimic block description 16550 mimic register set 4 8 host addr decode host data bus rx timer z80180 irq & control 180 side control config register d a t a b u s z80180 address pc host irq 8 z80180 data bu s 6 pc irq 1 pc dma mailbox and i/o mailbox pc dma control selectable com port decode 10 pc side 4 tx timer
65 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic fifo description the receiver fifo consists of a 16-word fifo capable of storing eight data bits and three error bits for each charac- ter stored (figure 77). parity error, framing error and break detect bits are stored, along with the data bits, by copying their value from three shadow bits, which are write only bits for the z80180 mpu lsr address. the three shadow bits are cleared after they are copied to the fifo memory. in fifo mode, to write error bits into the receiver fifo, the mpu must first write the parity, framing and break detect status to the line status register (shadow bits) and then write the character associated into the receiver buffer. the data and error bits will then move into the same address in the fifo. the error bits become available to the pc side of the interface when that particular location becomes the next address to read (top of fifo). at that time they may either be read by the pc by accessing them in the lsr, or they may cause an interrupt to the pc interface if so enabled. the error bits are set by the error status of the byte at the top of the fifo but may only be cleared by reading the lsr. if successive reads of the receiver fifo are performed without reading the lsr, the status bits will be set if any of the bytes read have the respective error bit set. the pc interface may be interrupted when 1, 4, 8 or 14 bytes are available in the receiver fifo by setting bits 6 and 7 in the fcr (fifo control register, pc address 02h to the appropriate value. if the fifo is not empty, but below the above trigger value, a time-out interrupt is available if the receiver fifo is not written by the mpu or read by the pc by an interval determined by the character time-out timer. this is an additional timer with mpu access only which is used to emulate the 16550 4 character time-out delay. the timer receives the brg as its input clock. software must determine the correct values to program into the receiver time-out register and the brg to achieve the correct delay interval for time-out. these interrupts are cleared by the fifo reaching the trigger point or by resetting the time-out interval timer by fifo mpu write or pc read access. with fifo mode enabled, the mpu is interrupted when the receiver fifo is empty, corresponding to bit 5 being set in the ius/ip register (mpu access only). this bit corre- sponds to a pc read of the receiver buffer in non-fifo (16450) mode. the interrupt source is cleared when the fifo becomes non-empty or the mpu reads the ius/ip register. the transmitter fifo is a 16 byte fifo with pc write and mpu read access (figure 78). in fifo mode, the pc will receive an interrupt when the transmitter becomes empty corresponding to bit 5 being set in the lsr. this bit and the interrupt source are cleared when the transmitter fifo becomes non-empty or the iir register is read by the pc. on the mpu interface, the transmitted data available can be programmed to interrupt the mpu on 1, 4, 8 or 14 bytes of available data by seeing the appropriate value in the mpu fscr control register (mpu write only xxech) bits 6 and 7. a time-out feature exists, transmitter time-out timer, which is an additional 8 bit timer with brg as the input source. if the transmitter fifo is non-empty and no pc write or mpu read of the fifo has taken place within the timer interval, a time-out will occur causing a correspond- ing interrupt to the mpu.
66 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic fifo description (continued) w r i t e b u f f e r 16x8 data bits 16x3 error bits r e a d b u f f e r write pointer alu read pointer sync phi mpu_rd pc read lsr b2-b4 error 3 3 mpu write lsr shadow b2-b4 8 mpu databus (mpu side write) sync 8 5 pc side databus (pc side read) fifo control register pc irq pc_rd phi mpu side interface 16550 mimic or pc side interface phi mpu irq figure 77. receiver fifo block diagram
67 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog figure 78. transmitter fifo block diagram w r i t e b u f f e r 16x8 data bits r e a d b u f f e r write pointer alu sync phi pc_wr 8 phi pc irq sync 8 mpu rea d (data) fcr reg . mpu irq mpu_rd phi 16550 mimic or pc side interface 16550 mimic o r pc side interfac e read pointer 5 pc write
68 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic fifo description (continued) table 15. 16550 line status register error description how to set how to clear error in at least one data byte available at least one error in receiver when there are no more rcvr in fifo with one error fifo errors fifo *temt transmitter empty mpu writes a 1 mpu writes a 0 ? *thre transmitter holding when mpu has when holding register register is empty read or emptied is not empty the holding register break break occurs when mpu writes 1 there is a detect received data input pc-side read is held in logic-0 of the lsr for longer than a full word transmission framing received character mpu writes 1 there is a error did not have a valid pc-side read stop bit of the lsr parity received character mpu writes 1 there is a error did not have correct pc-side read even or odd parity of the lsr overrun overlapping received mpu makes there is a error characters, thereby two writes pc-side read destroying the to receiver of the lsr previous character buffer register ?data indicates complete mpu writes to empty receiver ready incoming data has rcvr fifo or or receiver fifo been received receiver buffer register notes: * the temt and thre bits take on different functions when temt/double buffer mode is enabled. ? these signals are delayed to host when using character emulation delay.
69 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 mimic synchronization considerations because of the asynchronous nature of the fifos on the mimic, some scheme of synchronization must be pro- vided to prevent conflict from the dual port accesses of the mpu and the pc. to solve this problem, i/o to the fifo is buffered, the buffers allowing both pc and mpu to access the fifo asynchronously. read and write requests are then syn- chronized by means of the mpu clock. incoming signals are buffered in such a way that meta-stable input levels will be stabilized to valid 1 or 0 levels. actual transfers to and from the buffers from and to the fifo memory are timed by the mpu clock. alu evaluation is performed on a different phase than the transfer to ensure stable pointer values. another potential problem is that of simultaneous access of the mpu and pc to any of the various mailbox type registers. this is solved by dual buffering of the various read/write registers. during a read access by either mpu or pc to a mailbox register, the data in the buffered slave register is not permitted to change. any write that might take place during this time will be stored in the input of the master register. the corresponding status/interrupt will be reset as appropriate based on the write having followed the read to the register. for example, the ius/ip bit for the lcr write will not be cleared by the mpu read of the lcr if a simultaneous write to the lcr by the pc takes place. instead the lsr data will change after the read access and ius/ip bit 3 will remain at logic 1. double buffering for the transmitter in 16450 mode the z80189 implements double buffering for the transmit- ter in 16450 mode and sets the temt bit in the lsr register automatically. if character delay emulation is being used (see figure 79): 1. the pc thre bit in the lsr register is set when the thr register is empty; 2. pc host writes to the 16450 thr register; 3. whenever the z80189 tsr buffer is empty and one character delay timer is in a time out state, the byte from the thr register is transferred to the tsr buffer; 4. restart character delay timer (timer reloads and counts down) with byte transfer from thr register to the tsr buffer; 5. whenever the tsr buffer is full, the temt bit in lsr register for mpu is reset with no delay; 6. mpu reads tsr buffer; 7. temt bit in lsr register for mpu is set with no delay whenever the tsr buffer is empty; 8. when the tsr buffer is read by mpu and thr register is empty and one character delay timer reaches zero the temt bit in the lsr register for host is set from 0 to 1. the pc thre bit in the lsr register is reset whenever the thr register is full and set whenever thr register is empty. mpu ireq and dma request for the transmit data is triggered whenever the tsr buffer is full and cleared whenever tsr buffer is empty. if character delay emulation is not used the temt bit in the lsr register is set whenever both the thr register and the tsr buffer are both empty. the host temt bit is clear if there is data in either the tsr buffer or thr register. disable this feature when 16550 fifo mode is enabled.
70 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog double buffering for the transmitter in 16450 mode (continued) 16450 thr register host write empty/full host & mpu thre = 1 0 byte transfer if: - thre=0; and - tsre = 1; and - character delay timer is timed out. note: timer reloads and counts down whenever data is transferred from thr to tsr. thr to tsr delay transfer tsr transmit shift reg. emulation empty/full (mpu temt) tsre = 1 0 host temt = 1 if - thre = 1 and - tsre = 1 and - emulation delay timer is timed out note: mpu sees tsr bit in the lsr register as temt bit added tsr buffer for the transmit data z80189 mimic dma consideration since the /hrxrdy and /htxrdy is removed in the z189, the mimic dma feature found on the z182 is not available on the z189. z80189 mimic design hint the mimic output drive capability has been increased to 16 ma on the z189. this may eliminate the need for buffering to the pc bus. figure 79. temt emulation logic implementation
71 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic interface registers the 16550 mimic interface is controlled by the mmc register. setting it allows for different modes of operation such as using the eight bit counters and which irq structure is used with the pc/xt/at. both counters are single pass and stop on a count of zero. their purpose is to delay data transfer just as if the 16550 uart had to shift the data in and out. this is provided to alleviate any software problems a high speed continuous data transfer might cause to existing software. if this is not a problem, then data can be read and written as fast as the two machines can access the devices. in fifo mode of operation, the timers are used to delay the status to the pc interface by the time that would be required to actually shift the characters out or in if an actual uart were present. bit 5 reserved as 0 bit 4 reserved as 0 bit 3 reserved as 0 bit 2,1 interrupt select (read/write) bits 2, 1 00 if both bits 2 and 1 are set to zero, then the active hintr1 pin is set to normal 16550 mimic mode. 01 if bit 2 is zero and bit 1 is one, then the 16550 mimic will enable a wire and condition on the active hintr1 pin to the pc/xt/at. 10 if bit 2 is one and bit 1 is zero, then the active hintr1 pin will be driven only if out 2 of the modem control register is a one. if out 2 is a zero, then the active hintr1 pin will be tri-stated. 11 both bits should never be set to one. this is a reserved condition and should not be used. bit 0 vector include status (read/write) this bit is used to select the interrupt response mode of the z180. a 0 in this bit enables mode 0 interrupts; a 1 enables mode 2 response. 00000000 vis vector include status 0 = mode 0 interrupts 1 = mode 2 interrupts 7 65 4 321 0 hintr1 00 = normal 01 = wire and 10 = out 2 control 11 = reserved reserved as 0 reserved as 0 reserved as 0 rx timer enable tx timer enable figure 80. mimic master control register (z180 mpu address xxffh) bit 7 transmit timer delay counter enable (read/write) if bit 7 is set to a one, it enables the transmit delay timer. when the z180 reads the transmit register, the transmit delay timer is automatically loaded with the transmit time constant register and the timer is enabled to countdown to zero. this timer delays setting the transmitter holding register empty (thre) bit until the timer times out. if this bit is zero, then thre is set immediately on a z180 read of the transmit register. bit 6 receive timer delay counter enable (read/write) if bit 6 is set to a one, it enables the receive delay timer. when the z180 writes to the receive buffer, it loads the receive delay timer from the receive time constant reg- ister and enables the timer to countdown to zero. this timer delays setting the data ready (dr) bit in the lsr until the timer times out. if this bit is a zero, then dr is set immedi- ately on a z180 write to the receive buffer.
72 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 16550 mimic interrupt registers ius/ip register the ius/ip register is used by the z180 mpu to determine what has caused the interrupt. this register will have the appropriate bit set when an interrupt occurs. bit 5 transmitter time-out with data in fifo (read only) this bit is set when the transmitter fifo has been idle (no read or write and timer decrements to zero) with data bytes below the trigger level. it is cleared when the fifo is read or written. bit 4 receive buffer read (read only) this bit is set when the pc/xt/at reads the receive buffer register. it is reset when the z180 mpu writes to the receive buffer register. in fifo mode, this bit is set upon the pc reading all the data in the receiver fifo. note: rbr is set and interrupts when the receiver fifo has been emptied by the pc. this bit and interrupt are cleared when one or more bytes are written into the receiver fifo by the mpu. bit 3 modem control register write (read only) this bit is set when the pc/xt/at writes to the modem control register. it is reset when the z180 mpu reads the modem control register. bit 2 line control register write (read only) this bit is set when the pc/xt/at writes to the line control register. it is reset when the z180 mpu reads the line control register. bit 1 divisor latch ls/ms write (read only) this bit is set when the pc/xt/at writes to the divisor latch least significant or most significant bytes. it is reset when the pc reads the ls/ms register(s). to determine which byte(s) have been written, the z180 must read either ls or ms locations and then repoll this bit. if only one location is interrupting, the interrupt will be cleared when that location is read by the z180. bit 0 fifo control register write (read only) this bit is set when the pc/xt/at writes to the fcr. it is reset when the z180 mpu reads this register. 00010000 interrupt pending 6 thr write 5 tto transmitter timeout 4 rbr read 3 mcr write 2 lcr write 1 dll write 1 dlm write 0 fcr write or tx overrun 7 65 4 321 0 interrupt under service (rd) reset highest ius (wr) figure 81. ius/ip register (z180 mpu address xxfeh) bit 7 interrupt under service (read/write) this bit represents a logical or of each individual ius bit for the internal mimic interrupt daisy chain. an ius bit is set when an interrupt is registered (ip set) and enabled (ie set), the incoming iei daisy chain is active (chain enabled) and an interrupt acknowledge cycle is entered. by writing a 1 to this bit the highest priority ius bit that is set will be reset. writing a 0' to this bit has no effect. bit 6 transmitter holding register written (read only) this bit is set when the pc/xt/at writes to the transmitter holding register. it is reset when the z180 mpu reads the transmitter holding register. in fifo mode, this bit is set when the trigger level is reached (4, 8, 14 bytes available). if thr timer is enabled, this interrupt is delayed by the number of character times programmed as the trigger level. note: the thr bit is set (interrupts) when the transmitter fifo reaches the data available trigger level set in the mpu fscr control register. the bit and interrupt source is cleared when the number of data bytes falls below the set trigger level.
73 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog interrupt enable register the ie register allows each of the 16550/8250 interrupts to the z180 mpu to be masked off individually or globally. priority of interrupts are in this order: highest 6. thr irq 5. tto irq 4. rbr irq 3. mcr irq 2. lcr irq 1. dll irq 1. dlm irq lowest 0. fcr irq interrupt vector register the interrupt vector register contains either the opcode or the lower address for a z180 interrupt, depending upon the vis bit in the mmc register. if the vis bit is a zero, then z180 mode 0 interrupt is selected, if the vis bit is a one then z180 mode 2 is selected. figure 82. ie register (z180 mpu address xxfdh) bit 7 master interrupt enable (read/write) if bit 7 is a zero, all interrupts from the 16550 mimic are masked off. if this bit is a one, then interrupts are enabled individually by setting the appropriate bit. bit 6 enable thr interrupt (read/write) if this bit is a one, it enables the transmitter holding register interrupt. bit 5 enable tto interrupt (read/write) if this bit is a one, it enables the transmitter time-out interrupt. this will interrupt the cpu when characters remain in the fifo below the trigger level and the fifo is not read or written for the length of time in the transmitter time-out register. bit 4 enable rbr interrupt (read/write) if this bit is a one, it enables the receiver buffer register interrupt. bit 3 enable mcr interrupt (read/write) if this bit is 1, it enables the modem control register interrupt bit 2 enable lcr interrupt (read/write) if this bit is a one, it enables the line control register interrupt. bit 1 enable dll/dlm interrupt (read/write) if this bit is 1, it enables the divisor latch least and most significant byte interrupts bit 0 enable fcr interrupt (read/write) if this bit is a one, then interrupts are enabled for a pc write to the fifo control register (fcr). figure 83. ivec register (z180 mpu address xxfch) bit 7-4 upper nibble ivec (read/write) these four bits are to generate either an opcode or the upper four bits of the eight bit address to support the z180 interrupt modes. these bits are read/write and always read back what was last written to them. bits 3-1 status/opcode (read/write) these three bits are the interrupt status bits when vis in the mmc register is a one. if the vis bit is a zero, then these bits contain what was last written to them. bits 321 000 no irq 001 fcr irq 010 dll/dlm irq 011 lcr irq 100 mcr irq 101 rbr irq 110 tto irq 111 thr irq 00000000 0/opcode 7 65 4 321 0 upper nibble ivec status/opcode 00000000 interrupt enable 6 enable thr irq 5 enable tto irq 4 enable rbr irq 3 enable mcr irq 2 enable lcr irq 1 enable dll/dlm irq 0 enable fcr irq 7 65 4 321 0 mie
74 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog interrupt vector register (continued) bit 0 opcode (read/write) this bit is always a zero when the vis bit is a one. if the vis bit is a zero, then this bit reads back what was last written to it. this register serves both interrupt modes. when the vis bit is a zero, the last value written to the register can be read back. if the vis bit is a one and an interrupt is pending, the value read will be the last value written to the upper nibble plus the status for the interrupt that is pending. if no interrupt is pending, then the last value written to the upper nibble plus the lower nibble will be read from the register. if the vector includes the status, then the lower four bits of the vector will change asynchronously depending on the interrupting source. since this vector changes asynchro- nously, then the interrupt service routine to read the ivec register might read the source of the most recent irq/ intack cycle if that irq does not have its ius set. figure 84. fifo status and control register (z180 mpu read/write add xxech) bit 7 and bit 6 xmit trigger msb, lsb this field determines the number of bytes available to read in the transmitter fifo before an interrupt will occur to the mpu: b7 b6 level (#bytes) 001 014 108 1114 bit 5 receiver time-out enable this bit enables the z80189 receiver time-out timer that is used to emulate the four character time-out delay that is specified by the 16550. an rto interrupt will occur under the following conditions: no read or write to the rcvr fifo, data bytes are available, but below the pc trigger level, or the receiver timeout timer reaches zero. bit 4 transmitter time-out enable this bit enables the z80189 timer that is used to interrupt the z180 mpu if characters are available, but are below the trigger level. the timer is enabled to count down if this bit is one and the number of bytes is below the set transmitter trigger level. the timer will time-out and interrupt the mpu if no read or write to the xmit fifo takes place within the timer interval. bit 3 reserved for future use always write and read as 0 by users. writing 1 enables a test mode for emulation timers. bit 2 double buffer mode (write/read) (reset value=0) setting this bit will enable (only in 16450 mode) the temt hardware emulation and transmitter double buffering. double buffer this enables a transmit shift register (tsr) to act as a slave register, while the pc writes to a transmit holding register. the z180 reads from the transmit shift register. this allows the pc to write two consecutive bytes into the mimic. temt emulation if character delay emulation is being used, the temt is set as follows: the tsr is emptied and the associated delay logic has set the (delayed) thre bit in the lsr. at this time a one character delay timer begins. after this timer reaches zero count, the temt bit will be set if the thr and tsr output buffer are empty. temt is clear whenever there is data in either thr or the tsr output buffer. bit 1 receive timeout to the pc host (write/read) (reset value=0) setting this bit will enable the rto timeout to emulate the 16550 device. if enabled, the rto timer will not start timeout until all delayed characters have been clocked through the receiver character delay emulation logic. this will prevent an rto from occurring before a (delayed) receiver trigger level interrupt. when cleared, the rto will begin timeout from the last read or write to the receiver fifo. 00000000 force_450 7 65 4 321 0 receive timeout to pc host enable temt_dblbuff reserved (always 0) xmit timeout enable rcvr timeout enable xmit trigger (lsb) xmit trigger (msb)
75 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog bit 0 force 16450 mode (write/read) (reset value=0) this bit=1 will force the mimic into 16450 mode. bit 0 in the fcr reg is forced to zero as well as the mimic internal fifo enable. bits 7 and 6 in the iir will remain at their last value when this bit is set. 1 rec timeout constant 7 65 4 321 0 1111111 figure 85. receiver time-out timer constant (z180 mpu add xxeah) this register contains an 8-bit constant for emulation of the 16550 4 character time-out feature. software must deter- mine the value to load into this register based on the bit rate and word length specified by the mimic interface with the pc. this timer receives its input from the brg clock. this timer is enabled to down count when the enable bit in the fscr register is set and the trigger level has not been reached on the rcvr fifo. the counter will reload each time there is a read or write to the rcvr fifo. 11111111 transmitter timeout constant 7 65 4 321 0 figure 86. transmitter time-out timer constant (z180 mpu add xxebh) this register contains an 8-bit constant for determining the interval for the transmitter time-out timer. if allowed to decrement to zero, this timer will interrupt the mpu by setting the thr bit in the ius/ip register. this timer re- ceives its input from the brg clock. the timer is enabled to down count when the enable bit in the fscr register is set and the trigger level has not been reached on the xmit fifo. the counter will reload each time there is a read or write to the xmit fifo. transmit and receive timers because of the speed at which data transfers can take place between the z180 mpu and the pc/xt/at, two timers have been added to alleviate any software prob- lems that a high-speed data transfer might cause. these timers allow the programmer to slow down the data trans- fer just as if the 16550 mimic interface had to shift the data in and out. the timers receive their input from the brg clock. this allows the programmer access to a 24-bit timer to slow down the data transfer. 11111111 transmitter time constant 7 65 4 321 0 figure 87. transmitter time constant register (z180 mpu address xxfah) when a write from the pc/xt/at is made to the transmitter holding register, an interrupt to the z180 mpu is gener- ated. the z180 mpu then reads the data in the transmitter holding register. upon this read if the transmitter timer is enabled, the time constant from the transmitter time constant register is loaded into the transmitter timer and enables the count. after the timer reaches a count of zero, the transmitter holding register empty bit is set. however, the above is only true when the pc/xt/at is reading the transmitter holding register empty bit. to allow the z180 mpu to know that it has already read the byte of data, a mirrored transmitter holding register empty bit is set immediately following a read from the transmitter holding register. this mirrored bit is always read back to the z180 mpu when it reads the line status register. if the transmit- ter timer is not enabled when the z180 mpu reads the transmitter holding register, then both transmitter holding register empty bits are set immediately. in fifo mode of operation, the effect is similar in that the status to pc is always delayed such that a pc interrupt for empty fifo will not occur before the time required for each character read from the fifo by the z180 has elapsed. the effect is that the pc will not see data requests from an empty fifo any faster than would occur with a true uart when the delay feature is enabled. this timer is also used to delay data transfer from thr register to z80189 tsr buffer in double buffer mode.
76 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog transmit and receive timers (continued) enabled and counts down to zero. when the timer reaches zero, the data ready bit in the line status register is set. as with the transmit timer the data ready bit is also mirrored. immediately upon a write to the receive buffer, the mirrored bit is set to let the z180 mpu know that the byte has already been written. if the timer is not enabled, then both data ready bits are set immediately upon a write to the receive buffer. the fifo mode of operation is similar in that the status to the pc is always delayed by the time required for each character written to the fifo by the z180. the effect is that the pc will not see a fifo trigger level or dma request faster than would occur with a true uart when the delay feature is enabled. 16550 mimic registers the z80189 contains a register set for interfacing with the pc/xt/at. the registers are: receiver buffer register transmit holding register interrupt enable register interrupt identification register line control register modem control register line status register modem status register scratch register divisor latch least significant/most significant bytes fifo control register mimic modification register these registers are used to emulate the 16550 uart. the pc/xt/at can access these registers just as if it was interfacing with the 16550 uart. this allows the z80189 to be software compatible with existing z80189 modem software. receive buffer register when the z180 has assembled a byte of data to pass to the pc/xt/at, it places it in the receiver buffer register. if the received data available interrupt is enabled, then an interrupt is generated for the pc/xt/at and the data ready bit is set (if the receiver timer is enabled, the interrupt and setting of the data ready bit is delayed until after the timer times out). also, the shadow bits of the line status register are transferred to their respective bits when the z180 mpu writes to the receiver buffer register (see line status register bits 1, 2, 3 and 4). this allows a simultaneous setting of error bits when the data is written to the receiver buffer register. in fifo mode, this address is used to read (pc) and write (z180) the receiver fifo. figure 89. receiver buffer register xxxxxxxx receiver buffer register 7 65 4 321 0 pc read only, (address 00h, dlab=0, r/w=read) (z180 mpu write only, address xxf0h) 11111111 receiver time constant 7 65 4 321 0 figure 88. receiver time constant register (z180 mpu address xxfb) when the z180 mpu writes to the receive buffer register and the receive timer is enabled, the receive timer is loaded with the receiver time constant, the timer is
77 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog transmit holding register when the pc/xt/at writes to the transmitter holding register, the z80189 responds by setting the appropriate bit in the ip register and by generating an interrupt to the z180 mpu if it is enabled. when the z180 mpu reads this register, the transmitter holding register empty flag is set (if the transmitter timer is enabled, this bit is set after the timer times out). in fifo mode of operation, this address is used to read (z180) and write (pc) the transmitter fifo. xxxxxxxx transmitter holding register 7 65 4 321 0 (pc write only, address 00h, dlab=0, r/w=write) (z180 mpu read only, address xxf0h) figure 90. transmitter holding register fifo control register figure 91. fifo control register 00000000 fifo enable 7 65 4 321 0 rcvr fifo reset xmit fifo reset reserved (must be 0) reserved (tx overrun, mpu only) reserved (fcr write, mpu only) rcvr trigger (lsb) rcvr trigger (msb) pc/xt/at write only, pc address 02h z180 mpu read only, mpu address xxe9h bit 6 and bit 7 rcvr trigger lsb and msb bits this 2-bit field determines the number of required bytes in the receiver fifo before an interrupt to the pc occurs. b7 b6 trigger level, number of bytes 00 01 01 04 10 08 11 14 bit 4 and bit 5 reserved note: from the mpu side, bit 4 and bit 5 flag two sources of interrupts. bit 5 is a fifo interrupt, indicating that the fcr had changed; bit 4 is a tx overrun interrupt, indicating transmit overrun. a read of the fcr from the mpu side will clear a previously set bit 4 or bit 5. bit 3 reserved reserved for future use. bit 2 xmit fifo reset setting this bit to a 1 will cause the transmitter fifo pointer logic to be reset; any data in the fifo will be lost. this bit is self clearing; however, a shadow bit exists that is cleared only when read by the z180 mpu, allowing the mpu to monitor a fifo reset by the pc. bit 1 rcvr fifo reset setting this bit to a 1 will cause the receiver fifo pointer logic to be reset; any data in the fifo will be lost. this bit is self clearing; however, a shadow bit exists that is cleared only when read by the z180 mpu, allowing the mpu to monitor a fifo reset by the pc. bit 0 fifo enable the pc writes this bit to logic 1 to put the 16550 mimic into fifo mode. this bit must be a 1 when writing to the other bits in this register or they will not be programmed. when this bit changes state, any data in the fifos or transmitter holding and receiver buffer registers is lost and any pend- ing interrupts are cleared.
78 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog interrupt identification register mimic modification register 00000000 reserved - program to zero d7 d6 d5 d4 d3 d2 d1 d0 16550/450 rcvr overrun figure 92. mimic modification register (z189 mpu write only, address xxe9h) bit 7-2 reserved. program to zero. bit 1 rcvr overrun modification the actual 16450/16550 device allows the last position in fifo to be overwritten by mpu during receiver overrun condition. when this bit is enabled (programmed to 1) the last position in fifo can be overwritten by z180 during receiver overrun. this feature is disabled by default. when this modification is not enabled, the mimic will ignore any write to rbr during an overrun condition. bit 0 reserved program to zero. 00000000 0 if interrupt pending 7 65 4 321 0 interrupt id bit (0) interrupt id bit (1) interrupt id bit (2) always 0 fifo enabled flag pc/xt/at read only, pc address 02h z180 mpu no access figure 93. interrupt identification register bit 7 and bit 6 fifos enabled these bits will read 1 if fifo mode is enabled on the mimic. bit 5 and bit 4 always read 0 reserved bits. bits 3-1 interrupt id bits this 3 bit field is used to determine the highest priority interrupt pending. see table 16 for the 3-bit field descriptions. table 16. interrupt identification field b3 b2 b1 priority interrupt source inter. reset control 0 1 1 highest overrun, parity, read line stat. reg. framing error or break detect bits set by mpu. 0 1 0 2nd received data rcvr fifo drops below trigger level trigger level. 1 1 0 2nd receiver time-out read rcvr fifo. with data in rcvr fifo. 0 0 1 3rd transmitter writing to the holding register iir or transmitter empty. holding register. 0 0 0 4th modem status: reading the modem cts,dsr,ri or dcd.
79 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog bit 0 interrupt pending this bit is logic 0 and interrupt is pending. when the pc accesses the iir, the contents of the register and all pending interrupts are frozen. any new interrupts will be recorded, but not acknowledged during the iir access. line status register 00010000 data ready 7 65 4 321 0 overrun error parity error framing error break interrupt (bi) thre temt error in rcvr fifo pc/xt/at read only, pc address 05h z180 mpu read/write bits 6,4,3,2 mpu address xxf5h figure 94. line status register bit 7 error in rcvr fifo in 16450 mode, this bit will read logic 0. in 16550 mode, this bit is set if at least one data byte is available in the fifo with one of its associated error bits set. this bit will clear when there are no more errors (or break detects) in the fifo. bit 6 transmitter empty this bit must be set or reset by the mpu by a write to this register bit. if double buffer mode is enabled this bit is set automatically by hardware whenever both thr buffer and tsr is empty. bit 5 transmitter holding register empty, thre this bit is set to one when either the thr has been read (emptied) by the mpu (16450 mode) or the xmit fifo is empty (16550 mode). this bit is set to 0 when either the thr or xmit fifo become non-empty. a shadow bit exists so that the register bit setting to 1 is delayed by the transmitter timer if enabled. the mpu when reading this bit will not see the delay. both shadow and register bits are cleared when the pc writes to the thr of xmit fifo. note: the thre bit is forced to 0 in the pc side to prevent thr overruns when /halt is asserted (powerdown mode) and bit 3 (/into assertion on mimic access feature) is set. when the mimic comes out of powerdown (/halt deasserted), the thre bit resumes normal functionality. bit 2, 3, 4 parity error, framing error, break detect these bits are written, indirectly, by the mpu as follows: the bits are first written to shadow bit locations when the mpu write accesses the lsr. when the next character is written to the receiver buffer or rcvr fifo, the data in the shadow bits is then copied to the lsr (16450 mode) or fifo ram (16550 mode). in fifo mode, the bits become available to the pc when the data byte associated with the bits is next to be read (top of fifo). in fifo mode, with successive reads of the receiver, the status bits will be set if an error occurs on any byte. once the mpu writes to the receiver buffer or rcvr fifo, the shadow bits are auto cleared. the register bits are cleared upon the pc reading the lsr. in fifo mode, these bits will be set if any byte has the respective error bit set while the pc reads multiple characters from the fifo. bit 1 overrun error this bit is set if the z180 mpu makes two writes to the receiver buffer before the pc reads the data in the buffer (16450 mode) or with a full rcvr fifo (16550) mode. no data will be transferred to the rcvr fifo under these circumstances. this bit is reset when the pc reads the line status register. bit 0 data ready this bit is set to 1 when received data is available, either in the rcvr fifo (16550 mode) or receiver buffer register (16450 mode). this bit is set immediately upon the mpu writing data to the receiver buffer or fifo if the receiver timer is not enabled but is delayed by the timer interval if the receiver timer is enabled. for mpu read access, a shadow bit exists, so that the mpu does not see the delay the pc does. both bits are cleared to logic zero immedi- ately upon reading all the data in either the receiver buffer or fifo. interrupt enable register 00000000 bit 0 received data available int. 7 65 4 321 0 bit 1 thre interrupt bit 2 receiver line status int. bit 3 modem status interrupt bit 7,6,5,4 always 0 pc/xt/at read/write, pc address 01h z180 mpu read only, z180 mpu address xxf1h figure 95. interrupt enable register
80 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog bit 6-bit 0 these bits do not affect the z80189 directly; however, they can be read by the z180 mpu and the 16550 mimic modes can be emulated by the z180 mpu. modem control register interrupt enable register (continued) bits 7,6,5,4 reserved these bits will always read 0 (pc and mpu) bit 3 modem status irq if bits 0,1,2 or 3 of the modem status register are set and this enable bit is a logic 1, then an interrupt to the pc is generated. bit 2 receiver line status irq if bits 1,2,3 or 4 of the lsr are set and this enable bit is a logic 1, then an interrupt to the pc is generated. bit 1 transmitter holding register empty irq if bit 5 of the lsr is set and this enable bit is a logic 1, then an interrupt to the pc is generated. bit 0 received data available irq if bit 0 of the lsr is set or a receiver timeout occurs and this enable bit is a logic 1, then an interrupt to the pc is generated. line control register 00000000 dalb 7 65 4 321 0 set break even parity sel. parity enable pc/xt/at read/write, pc/xt/at address 3h z180 mpu read only, z180 mu address xxf3h number of stop bits word length sel. stick parity figure 96. line control register bit 7 divisor latch access bit (dalb) this bit allows access to the divisor latch by the pc/xt/at. if this bit is set to a one, access to the transmitter, receiver and interrupt enable registers is disabled, and when an access is made to address 0, the divisor latch least significant byte is accessed and if an access is made to address 1, the divisor latch most significant byte is accessed. 00000000 7 65 4 321 0 reserved loop out 2 pc/xt/at read/write, pc/xt/at address 4h z180 mpu read only, z180 mu address xxf4h out 1 dts rts figure 97. modem control register bit 7-5 reserved reserved for future use, always 0. bit 4 loop when this bit is set to a one then: ri = out 1 dcd = out 2 dsr = dtr cts = rts emulation of the loop back feature of the 16550 uart must be done by the z180 mpu except for the above conditions. bit 3 out 2 this bit controls the state on the active hintr pin if bits 2 and 1 of the mimic master control register are a 10. or else it can be read by the z180 mpu. bit 2-bit 0 these bits have no direct control of the 16550 mimic interface and the z180 mpu must emulate the function if it is to be implemented.
81 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog modem status register 00000000 dcts 7 65 4 321 0 ddsr teri ddcd cts dsr ri dcd pc/xt/at read only, pc/xt/at address 6h z180 mpu read/write bits 7-4, z180 mpu address xxf6h figure 98. modem status register bit 7 data carrier detect this bit must be written by the z180 mpu. bit 6 ring indicator this bit must be written by the z180 mpu. bit 5 data set ready this bit must be written by the z180 mpu. bit 4 clear to send this bit must be written by the z180 mpu. bit 3 delta data carrier detect this bit is set to a one whenever the data carrier detect bit changes state. this bit is reset when the pc/xt/at reads the modem status register. bit 2 trailing edge ring indicator this bit is set to a one on the falling edge of the ring indicator bit. this bit is reset when the pc/xt/at reads the modem status register. bit 1 delta data set ready this bit is set to a one whenever the data set ready bit changes state. this bit is reset when the pc/xt/at reads the modem status register. bit 0 delta clear to send this bit is set to a one whenever the clear to send bit changes state. this bit is reset when the pc/xt/at reads the modem status register. scratch register figure 100. divisor latch (ls) bit 7-0 divisor latch most significant (ms) this register contains the low order byte of the baud rate divisor. writing to this register with the pc/xt/at will generate an interrupt to the z180 mpu. it can then read the baud rate divisor and set up the application. divisor latch (ms) figure 101. divisor latch (ms) bit 7-0 divisor latch most significant (ms) this register contains the high order byte of the baud rate divisor. writing to this register with the pc/xt/at will generate an interrupt to the z180 mpu. it can then read the baud rate divisor and set up application. xxxxxxxx scratch register 7 65 4 321 0 pc/xt/at read/write, pc/xt/at address 07h z180 mpu read only, z180 mpu address xxf7h figure 99. scratch register bits 7-0 scratch register this register is used by the pc/xt/at programmer for temporary data storage. the z180 mpu is able to read this register. if the pc/xt/at writes to this register, no interrupt to the z180 mpu is generated. divisor latch (ls) xxxxxxxx divisor latch (ls) 7 65 4 321 0 pc/xt/at read/write, pc/xt/at address 00h and dlab = 1 z180 mpu read only, z180 mpu address xxf8h xxxxxxxx divisor latch (ms) 7 65 4 321 0 pc/xt/at read/write, pc/xt/at address 01h and dlab = 1 z180 mpu read only, z180 mpu address xxf9h
82 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc dma mailbox general description the concept behind the pc dma mailbox registers is to provide a path for the pc dma data transfer separate from the mimic com port. commands and data flow over the com port, while the dma path is reserved for other purposes. the pc dma mailbox register functionality will require control registers which will allow pc dma data transfer between the pc memory and for example, a modem speaker/microphone codec. note that the transfer will be driven by the pc host dmas. this feature only allows for the handshaking and data path for the pc host dmas. the host (pc) dma channels will use the following four z189 pins for the pc dma mailbox feature. each pair of pins are individually selectable: hdrq0 host dma request 0, z189 output, active high, high-z control /hdack0 host dma acknowledge 0, z189 input, active low hdrq1 host dma request 1, z189 output, active high, high-z control /hdack1 host dma acknowledge 1, z189 input, active low the pins labeled as hdrq0 and hdrq1 are asserted by the z180 to signal the pc host of a dma request. the pins labelled /hdack0 and /hdack1 are asserted by the pc to signal a pc dma access. dual request/acknowledge pairs are provided to interface with two pc dma channels. the pc mailbox channels are independent and can be used simultaneously or individually for jumperless dma channel selection. pc dma mailbox bit functions hdreq. host dma request bit, default value = 0 two bits will serve to request a pc host dma access. when this bit is set and the host dma channel is enabled (hdmae=1), the corresponding hdrq pin will be as- serted high. z180 software sets this bit (out0 instruction) to request a dma transfer, and z189 hardware clears the bit when the byte transfer is complete. z180 software can also clear the bit. the z180 will be able to read the bit (in0 instruction) to indicate that the transfer has occurred. i/o address of xxd2h (hmc register) contains a request bit for each dma channel (bit 4 and bit 5 of the hmc register). write enable bits are provided to simplify code (read-modify-write cycles not required). hdmae host dma enable default=0, hdrq is tri-stated two bits will serve to enable the dual dma channels request/acknowledge pairs. when the hdmae1 bit is set, the output will become fully driven, otherwise (hdmae1 bit is reset) the hdrq1 will be tri-stated. when the hdmae0 bit is set the hdrq0 output will become fully driven, otherwise, the hdrq0 output will be tri-stated. i/o address xxd2h is assigned the hmc register. bits 0 and 1 of the hmc register are respectively assigned hdmae0 and hdmae1.
83 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 3. z189 hardware forces hdrq inactive low on the leading (falling) edge of /hwr during the /hdack cycle. note that the hdreq register bit is not to be cleared yet, since the dma cycle has not yet com- pleted. 4. the pc places valid data on the isa bus (hd[0:7] and asserts /hwr low. 5. z189 hardware latches data into the hdmat register on the trailing (rising) edge of /hwr while /hdack is still active low. on this same edge, hardware clears the hdreq register bit. 6. z180 software polls the hdreq bit until it's 0, and then can input the data byte from hdmat. the polling of the hdreq bit is used to indicate when the pc dma write has been completed. the pc software program should program its dma controller to stop dma at the end of valid data or when commanded by the application. when the z180 software sets hdreq, but doesn't see the hdreq bit automatically cleared within a reason- able time (because /hdack remains inactive high), then software can stop the pc dma write by resetting the hdreq bit. 7. messages on the com port confirm that the pc dma write operation is complete. z180 software clears hdreq, then clears hdmae to disable host dma. pc dma read pc dma read is almost the same as a pc dma write, but the data flows the other direction through the hdmar register. through commands exchanged over the mimic com port, pc software and the z180 agree to configure dma for a pc dma read, in which data flows from, for example, a modem's microphone codec to pc memory. the pc sets up its 8237 dma controller in auto-initialize mode to assure that there is always buffer space available whenever the modem makes a dma request. the z180 clears hdreq and sets hdmae, forcing hdrq low. the pc dma read proceeds as follows: 1. z180 software outputs the data byte to hdmar, where it is latched. 2. z180 software writes a 1 to the hdreq bit, causing the hdrq pin to go active high. pc mailbox data registers hdmat0 host dma transmit register 0, z180 read only, pc write only hdmat1 host dma transmit register 1, z180 read only, pc write only hdmar0 host dma receive register 0, z180 write only, pc read only hdmar1 host dma receive register 1, z180 write only, pc read only there are four separate 8-bit mailbox registers available for dma data. the i/o address for the mailbox registers will be xxdoh for mailbox 0 and xxd1h for mailbox 1. note that there are separate registers for read and write access. the mailbox register can latch data from the host data bus hd[0:7] and is readable by the z180 using in0 a, (doh) or in0 a, (d1h). data can be written into the mailbox registers using the out0 (doh), a or out0 (d1h), a and can output its contents onto hd [0:7} during a pc host dma access. note: the following is a description of other z189 signals relevant in a pc dma mailbox access. C the /hddis signal will go low during a pc dma read access (selected /hdack and /hrd going low). C the /hcs pin will not asserted low during a pc dma mailbox access (/hdack active) if the hdrq/hdack channel is enabled. pc dma write through commands exchanged over the mimic com port, pc software and the z180 agree to configure dma for a pc dma write, in which data flows from pc memory to, for example, a modem's speaker codec. the pc sets up its 8237 dma controller in auto-initialize mode to assure that data is always available whenever the modem makes a dma request. the z180 clears hdreq and sets hdmae, forcing hdrq low. the pc dma write proceeds as follows: 1. z180 software writes a 1 to the hdreq bit, causing the hdrq pin to go active high. 2. the rising edge of hdrq causes the 8237 dma controller to begin a memory-read, i/o-write dma bus cycle on the isa bus at the end of the current pc bus cycle. the pc asserts /hdack low to acknowledge the dma request.
84 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc mailbox data registers (continued) 3. the rising edge of hdrq causes the 8237 dma controller to begin an i/o-read, memory-write dma bus cycle on the isa bus at the end of the current pc bus cycle. the pc asserts /hdack low to acknowl- edge the dma request. 4. z189 hardware forces hdrq inactive low on the leading (falling) edge of /hrd during the /hdack cycle. note that the hdreq register is not to be cleared yet, since the dma cycle has not completed. 5. the pc asserts /hrd low while /hdack is still active low, causing z189 hardware to enable the latched hdmar byte onto hd[0:7]. 6. while z189 hardware holds valid data on the isa bus, the pc does its memory-write half of the dma cycle. on the trailing (rising) edge of /hrd, z189 hardware disables the output of the hdmar register, putting hd[0:7] in high impedance state. on this same edge, hardware clears the hdreq register bit. note: /hddis will go low while the hdmar register is accessed on the isa bus. 7. z180 software polls the hdreq bit until it's 0, then continues with step 0 for the next byte. pc dma read will not be stopped as with the case for pc dma write if the hdreq handshake is not met. if software fails to see hdreq reset soon after making the dma request (because /hdack remains inactive high), z180 software should clear hdreq and hdmae and configure the data pump to stop the pc dma read. logic equations for pc dma read/write this section summarizes the significant events for pc dma read/write that was explained in the previous sections. this section can be used as a quick check of the circuit implementation. set hdreq bit: i/o write 1 to hdreq bit in hmc register. clear hdreq bit: reset or i/o write 0 to hdreq bit in hmc register or (rising edge of (/hrd and /hwr) while /hdack=0) drive hdrq pin active high: hdreq bit = 1 while hdmae=1 drive hdrq pin inactive low: reset or /hdack=0 or hdreq bit = 0 latch pc dma write data to hdmat register: hdmae=1 and /hdack=0 and /hwr=0 drive pc dma read data from hdmar register: hdmae=1 and /hdack=0 and /hrd=0 selectable dma channels the z189 features jumperless selection of pc dma chan- nels. on the 8-bit pc/xt bus, dma channels 0 and 3 are generally available, therefore reference designs may con- nect to those. 2 hdreq bits and 2 hdmae enable bits are used to enable which pc dma channel is to be imple- mented. in addition, there are two additional bits which allow for the multiplexing of pc dma mailbox functions with bus mastering and z180 peripheral functions. pc dma mailbox pin designations the four request/acknowledge pins will be designated as follows, and are assigned the following qfp pins as shown below: hdrq, pin 50, output (mux with rts0) /hdack0, pin 43, input (mux with cka0 and /dreq0) hdrq1, pin 97, output (mux with /busack) /hdack1, pin 98, input (mux with /busreq)
85 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc mailbox data registers (continued) 11000000 7 65 4 321 0 0 = hdrq0 tri-state 1 = hdma enable 0 = hdrq1 tri-state 1 = hdma enable hdrq /hdack0, cka0//dreq0, /rts0 0 = hdrq0, /hdack0 select 1 = /rts0, cka0//dreq0 select hdrq1, /hdack1, /busack, /busreq 0 = hdrq1, /hdack1 select 1 = /busack, /busreq select hdreq0 (dma request 0) hdreq1 (dma request 1) revision data avail write enable hdreq0 revision data avail write enable hdreq1 figure 102. host dma mailbox control register, hmc (z180 mpu read/write address xxd2h) bits 7 write enable hdreq1 (write only) revision data available (read only) set this bit whenever setting/resetting the hdreq1 bit. when this bit is written with 1, bit 5 will be written into the hdreq bit and bits 0-3 are ignored. when this bit is written with zero, bits 0-3 can be written and bit 5 is ignored. note that this bit does not change the write access to bits 4 and 6. the write enable is not latched and must be set for each hdreq1 write. when bit 7 is read it is set upon powerup and becomes reset during the 1st read of the hdmat1 register. bits 6 write enable hdreq0 (write only) set this bit whenever setting/resetting the hdreq0 bit. when this bit is written with 1, bit 4 will be written into the hdreq0 bit and bits 0-3 are ignored. when this bit is written with zero, bits 0-3 can be written and bit 4 is ignored. note that this bit does not change the write access to bits 5 and 7. the write enable is not latched and must be set for each hdreq0 write. when bit 6 is read, it indicates the availability of the revision data in the host dma transmit register (hdmat0). when the revision data is read by the z180 cpu, this bit will become reset and the revision data will no longer be available in the hdmat0 register. bit 5 hdreq1 bit when mailbox 1 is multiplexed and enabled (hdmae1=1), setting this bit will cause the hdrq1 pin to go active high, which puts out a request to the pc for a dma transfer. z189 hardware clears this bit when byte transfer is complete. this bit is disabled upon reset. this bit can also be reset to force the hdrq1 pin to inactive low. note that bit 7 must be set to modify hdreq1. bit 4 hdreq0 bit when mailbox 0 is multiplexed and enabled (hdmae0=1), setting this bit will cause the hdrq0 pin to go active high, which puts out a request to the pc for a dma transfer. z189 hardware clears this bit when byte transfer is complete. this bit is disabled upon reset. this bit can also be reset to force the hdrq0 pin to inactive low. note that bit 6 must be set to modify hdreq0. bit 3 hdrq1/hdack1, /busack /busreq this bit selects the multiplexing that will occur between the hdrq1//busack and the /hdack1/busreq pins. if this bit is set to 0, the hdrq1 and /hdack1 functions are enabled for this pin. otherwise, if this bit is set to 1, the /busack and /busreq functions are enabled for this pin. this bit is reset to 0. bit 2 hdrq/hdack0, /rts0 cka0//dreq0 this bit selects the multiplexing that will occur between the hdrq0//rts0 and the /hdack/cka0//dreq0 pins. if this bit is set to 0, the hdrq and /hdack0 functions are enabled for this pin. otherwise, if this bit is set to 1, the cka0//dreq0 and /rts0 functions are enabled for this pin. this bit is reset to 0. bit 1 hdmae1 bit when this bit is set to 1, it allows mailbox 1 to request a pc dma cycle given that the mailbox 1 pins are multiplexed (bit 4=1). when this bit is cleared to 0, the hdreq1 is tri- stated if mailbox 1 pins are multiplexed. when this bit is cleared, the hdmat1 can be used to store host output mailbox data. bit 0 hdmae0 bit when this bit is set to 1, it allows mailbox 0 to request a pc dma cycle given that the mailbox 0 pins are multiplexed (bit 4=1). when this bit is cleared to 0, the hdreq0 is tri- stated if mailbox 0 pins are multiplexed.
86 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog pc dma mailbox data registers 10010001 7 65 4 321 0 figure 103. host dma transmit register, hdmat0 (z180 mpu read only address xxd0h) (pc write only) note: 91hex is defaulted into this register to indicate revision (9 for z189 and 1 for 1st revision). once the revision data is read by the z180 cpu, bit 6 of the hmc register (revision data avail bit) will be read as zero. 00000000 7 65 4 321 0 figure 105. host dma transmit register, hdmat1 (z180 mpu read only address xxd1h) (pc write only) hdmat1 can also be used as a host output mailbox data register. refer to host output mailbox function for details. 00000000 7 65 4 321 0 figure 106. host dma receive register, hdmar1 (z180 mpu write only address xxd1h) (pc read only) host input/output mailbox enhancements the purpose of host i/o mailbox is to provide an additional data path between pc host and z80189 in a modem control application. this is required in order to accommo- date transfer of data other than data (flows through com port) or audio (flows through pc dma mailbox). an example implementation of this feature is described below: C pc host controlled com port selection. in a psuedo "plug & play" environment, the pc bios will assign a modem to a com port address upon powerup. there- fore, the modem will need to "listen" to the pc bus for bios calls that query the existence of a modem card. 00000000 7 65 4 321 0 figure 104. host dma receive register, hdmar0 (z180 mpu write only address xxd0h) (pc read only) the modem will then need to reply and output informa- tion on its capabilities and requirements. the pc bios will then assign the modem to a com port and interrupt such that there are no resource conflicts. in order to facilitate the feature listed above, a communica- tion path needs to be available between a pc bios and modem prior to the selection of com port, dma, or irq selection.
87 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog enhancement detail pc host address selection. there are a total of 4 regis- ters addresses that are accessible by the pc host. they are as follows: address ha9-ha2 programmable function ha1 ha0 host output register 0 0 0 host output/input register 1 0 1 host i/o status register 1 0 *host output to hdmat1 register 1 1 the ha9-ha2 is programmable by writing the contents into port a data register. the pc host access will occur during a pc host input/output cycle at the programmed address range (/hrd or /hwr=0, haen=0, pa[9:2]=padata[7:0]). note: padata should be written with the address range prior to enabling this feature. * if the host dma mailbox 1 function is disabled (bit 1 of hmc register is zero), a host write in the programmed mailbox range with ha1,0=1,1, will cause the host data to be latched into the hdmat1 register. this can be used as an auxiliary host output register. note that a host read from this address is invalid. 00000000 7 65 4 321 0 figure 107. host output register 0 (hor0) (180 mpu read only address xxd3h) (pc host read/write ha9-2 (padata) + 00b) figure 108. host output register 1 (hor1) (180 mpu read only address xxd4h) (pc host write only ha9-2 (padata) +01b) 000 00000 7 65 4 321 0 host output register 1 data available host input register 1 data available auxilliary bits host i/o mailbox enable unlock bit host output register 0 data available figure 110. host i/o status register (hios) (180 mpu read/write address xxd5h) (pc host read only ha9-ha2 (padata) + 10b) bit 7. host i/o mailbox enable. the z180 must write a logic one to this bit to enable the host i/o mailbox. when this bit is at zero (default), host accesses are disabled. this bit is only writable by the z180, but is readable by both z180 and pc host. when this bit is zero, registers d3, d4 and d5 cannot be read or written except for a write to the enable bit in register d5 bit 7. also, when this bit is zero the host side is not accessible. once this bit is set, all registers become visible to the z180 and the host. note: the padata should be programmed with ha9:ha2 address range prior to setting this bit. this bit should be programmed as zero when the com decode mux (cdr bit 0) is disabled. bits 6-4. auxiliary bits. these bits can be written by the z180 and can be read by both the pc host and the z180. note that the pc host cannot write to these bits. the auxillary bits are zero by default and have no function other than to serve as scratch bits for the host i/o mailbox. bit 3. host input register 1 data available. this bit be- comes set when the z180 writes to the host input register 1. a pc host read of the host input register 1 will cause this bit to clear. this bit cannot be set unless the host i/o mailbox enable bit is set. bit 1. host output register 0 data available. this bit becomes set when the pc host writes to the host output register 0. a z180 read of the host output register 0 will cause this bit to clear. this bit cannot be set unless the host i/o mailbox enable bit is set. 00000000 7 65 4 321 0 00000000 7 65 4 321 0 figure 109. host input register 1 (hir1) (180 mpu write only address xxd4h) (pc host read only ha9-2 (padata) + 01b)
88 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog host input/output mailbox enhancements (continued) if com port decode is disabled and com port decode mux is enabled (default), com decode pins ha9-ha3, haen are ignored inputs. if hc1 is forced low the mimic data latch will be forced open. therefore, care should be taken that the hc1//hcs pin is never connected directly to logic high or low, when com port decode is disabled. /hcs pin can also be programmed as an output for debug purposes. when the /hcs force bit (bit 7 in the com port decode register) is enabled, the /hcs pin will be asserted low whenever the mimic is being accessed by the pc host. this feature is only available when the com port decode is enabled. a dual hintr option will provide two mimic interrupt requests to the host. hintr1 will be asserted during a mimic interrupt request when com decode is configured for com 1 & 3. hintr2 will be asserted during a mimic interrupt request when com decode is configured for com 2 & 4. the unasserted hintr line will be tri-stated. note that during initialization, the com decode regis- ter must be written to before the system configuration register. single baud rate generator a baud rate generator is included to provide emulation timing for the mimic device. this brg is very similar to escc brg in functionality. there are 2x8 bit registers to program the clock divider. the input to the brg is the phi clock output of the s180 core. the time constant required for a specific bit rate is as follows: time constant (decimal) = (phi freq. / (2*baud rate))-2 this formula is exactly the same as used in the escc. the output of the brg is directly connected to mimic emulation counter input. bit 0. unlock bit. when the host i/o mailbox is enabled, a pc host write to address 0fbhex will cause this bit to set. a pc host write to address 0f9hex will cause this bit to reset. the data written to these registers will not be stored. a read access or access with haen=1 will not cause this bit to toggle. note that this bit has no function other than a status bit (there is no locking or unlocking caused by the state of this bit). the state of the unlock bit is not controlled by the host i/o mailbox bit. any i/o write to fb will set the bit and a write to f9 will clear it regardless of the state of the host i/o mailbox enable bit. note that the data written to 0fbhex or 0f9hex will not be stored by the z189. i/o chip select w/prog. range the z80187 has two i/o chip selects labelled /iocs1 and /iocs2. the /iocs1 will have same function- ality as the z80182s /iocs pin (multiplexed with ieo and active during i/o accesses between ranges xx80h to xxbfh). the iocs pins will be asserted if /iorq is active, /m1 is inactive, and address compare is within range. the z80189 also has a secondary iocs labeled /iocs2. this pin will be active for i/o accesses in the range of xxc0h - xxc7h or xxc8h-xxcfh. the /iocs2 pin will be multiplexed over the e pin when enabled. com port decode com port decode allows mimic to be selected when pc address ha9-ha3 specifies a selected com port address range by hc pins 1 and 2 (selects com port address 1-4). hc1 and hc2 can be read in software and program an appropriate comport range for the decode circuitry. hc1 and hc2 can also be used for general input purposes. the status of these pins can also be read when the com decode mux is disabled.
89 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog baud rate generator register the following registers are used to store brg constant. the timer is enabled after setting bit 0 of iobrg register. design is such that on-the-fly modification of registers do not cause irregular brg output. lower byte of time constant 7 65 4 321 0 1111 1111 iobrg register the following register handles the iocs feature and mimic brg. iobrg-iocs & brg enable (address xxd6h) default 04 hex. 00000100 brg enable 7 65 4 321 0 /iocs2 range 1 = i/o access between xxc0h-xxc7 0 = i/o access between xxc8h-xxcf /iocs2 enable /into assertion of mimic access reserved as 0 figure 113. iobrg-iocs and brg enable (address xxd6h) bits 4-7 reserved bit 3 /int0 assertion on mimic access. when this bit r/w is enabled, and the /halt is active (power-down) any host access to the mimic will cause a low edge. since this interrupt source has no vector, /int0 mode 1 must be used when enabling this mode. this is disabled on power-up. /int0 asser- tion is released when /halt is deasserted. note: the thre bit is forced to 0 on the pc side to prevent thr overrun during powerdown modes when this feature is enabled. when the mimic comes out of power-down, thre resumes normal functionality. bit 2 /iocs2 enable when set, iocs2 is muxed over e pin. this is enabled on reset. bit 1 /iocs2 range. r/w when set, iocs2 is active during i/o accesses between xxc0h-xxc7h. when reset, iocs2 is active during i/o accesses between xxc8h-xxcfh. this is disabled on power-up. bit 0 brg enable. when set, r/w the mimic brg begins counting down to gener- ate a programmed square wave to the mimic emulation timers. this is disabled on power-up. note: when waking from standby mode using a pc-thr write, the thre bit will not reset until clock is stabilized. this may cause a thr overrun. therefore, data integrity cannot be guaranteed. care should be taken so that standby mode is only used when data integrity is not essential. figure 111. brgl baud rate generator low (address xxe0h) default 00 hex upper byte of time constant 7 65 4 321 0 1111 1111 figure 112. brgh baud rate generator high (address xxe9h) default 00 hex
90 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog host input/output mailbox enhancements (continued) 00000001 com port decode mux 7 65 4 321 0 state of hc1 (read only) com port decode selection bit 4 3 0 0 com 1 (3f8-3ff) default reserved as 0 0 1 com 2 (2f8-2ff) 1 0 com 3 (3e8-3ef) 1 1 com 4 (2e8-2ef) com port decode enable dual hintr state of hc2 decoder during a pc-dma cycle. this circuitry is not used when com port decode (bit 5) is dis- abled. ha2-ha0 are used to select between internal mimic registers. bit 5 com port decode enable. when this bit r/w is set, ha3-ha9 inputs are used for com port decoder. the mimic will be accessible given that the address inputs ha3-ha9 are within the range programmed by bits 3 & 4 when haen is active low. please refer to multiplexing section for de- tails on pin ha3-ha9 muxing. this is disabled on reset. when disabled, the com port de- code inputs are still treated as inputs, but have no affect on mimic operation. bit 6 dual hintr. when this bit is set, the r/w hintr2 output will be asserted for mimic interrupt requests when configured for com 2 & 4. hintr1 output will be asserted for mimic interrupt requests when configured for com 1 & 3. when disabled, hintr2 is always inactive (tri-stated) while hintr1 is active for all mimic interrupt requests. this is disabled on reset (hintr2 is tri-state on power-up). note that the unselected hintr line will be tri- stated while the active hintr line will be driven as per the mimic master control register bit 7 /hcs force bit. when bit 0 and bit 5 of this register is set to 1 (com decode mux and logic enabled), it forces the /hcs signal to be exported out of the /hcs/hc1 pin. /hcs output is asserted when ha3-ha9 is within the bound- aries programmed by bits 3-4 of cdr (regard- less of /hrd and /hwr). /hcs is not asserted for pc dma mailbox accesses. if this bit is zero (default), the /hcs/hc1 pin becomes an input. note: the /hcs/hc1 pin is tied to both /hcs function and hc1 functions simultaneously when bit 7 is reset to zero. therefore, mimic access is disabled until the first system configuration register write on com decode (bit 5) is enabled. this mechanism prevents accidental bus con- tention if /hcs/hc1 pin is pulled low. note: the com decode register must be written first, prior to the system configuration register during initializa- tion. figure 114. cdr - com decode register (address xxd7h) cdr - com decode register (address xxd7h) default 01hex bit 0 com port decode mux. when set, com port r/w decode pins (ha9-ha3, haen hc1-2) are enabled. this is set on default. refer to multi- plexing section for further detail. bit <1-2> read only registers that specify the state of hc1 and hc2 input pins when com port select feature is enabled in bit 0. bit 1 represents hc1 input. bit 2 represents hc2 input. since hc1 is multiplexed with /hcs, care should be taken that if com port decode is disabled, /hcs is not forced low. bit <3-4> com port decode selection. these two bits are used to select com port decode 1-4 as r/w follows: bit 4 bit 3 0 0 com 1 (3f8-3ff) default 0 1 com 2 (2f8-2ff) 1 0 com 3 (3e8-3ef) 1 1 com 4 (2e8-2ef) mimic access will only be allowed if inputs ha9- ha3 reflect the above address ranges and haen is deasserted. haen is used to disable the com the register that handles and enables com port decode and multiplexing is as follows:
91 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z189 miscellaneous control and interface registers the z80189 has the same capability of the z180 mpu. some extra i/o registers have been added to the z180 mpu to interface with the parallel ports, com port decode and the 16550 mimic interface. a system configuration register is located at the z180 mpu i/o address %ef which determines the current operating mode. this regis- ter must be written before the mimic is enabled. 11100111 reserved as 1 7 65 4 321 0 mimic/port a 0 = port a 1 = mimic data borrow 0 = z80180 1 = 16550 mimic disable roms 0 = /romcs enabled 1 = /romcs disabled dout 0 = no data out 1 = data out port pb4-pb0 select 0 = asci channel 0 function 1 = pb4-pb0 selected port pb7-pb5 select 0 = asci channel 1 function 1 = pb7-pb5 selected port c read select 0 = from output pad 1 = from input pins figure 115. system configuration register (z80180 mpu address xxefh) note: the com decode register should be written prior to writing to this register. bit 7 port c read when this bit is set, a read from port c will return value of logic state on port c. when this bit is reset, a read from port c will return the contents of port c output pads (last value output on port c). this bit is not relevant when port c is programmed for output. bit 6 pb7-pb5 select when this bit is set port b bits 7-5 are multiplexed over asci 1 functions. when this bit is reset asci 1 functions are active. bit 5 pb4-pb0 select when this bit is set port b bits 4-0 are multiplexed over asci 0 functions. when this bit is reset asci functions are active. bit 4 d dout rom emulator mode enable when this bit is set to a 1, the z182 is in rom emulator mode. in this mode, bus direction for certain transaction periods are set to the opposite direction to export internal bus transactions outside the z80189. this allows the use of rom emulators/logic analyzers for application develop- ment. see figures 115 and 116.
92 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog i/o write to on-chip peripherals i/o read from on-chip peripherals i/o write to off-chip peripherals write to memory write from memory refresh z80189 idle mode i/o and memory transactions z80189 data bus (ddout=0) z80189 data bus (ddout=1) out out z out out out out out in in z z z z i/o read from off-chip peripherals in in intack for on-chip peripheral intack for off-chip peripheral interrupt acknowledge transaction z80189 data bus (ddout=0) z80189 data bus (ddout=1) z out in in the word out means that the z189 data bus direction is in output mode, in means input mode, and z means high impedance. d dout stands for data direction out and is the status of the d4 bit in the system configuration register. bit 3 disable roms if this bit is a one it disables the /romcs pin. if it is a zero addresses below the rom boundary set by the rombr register will cause the /romcs pin to go low. bit 2 borrow for bit 2 of the system configuration register when the bit is set to 0, the hintr1/t out is multiplexed to t out . when this bit is set to 1, the hintr1/t out bit is multiplexed to hintr1. this bit is set to 1 upon reset. bit 1 mimic/port a when this bit is set, mimic is multiplexed over port a. this is enabled on power-up. bit 0 reserved note: mimic access is disabled until the first system configuration register write after power-up or reset. this mechanism prevents accidental bus counter from if /hdcs/hc1 pin is pulled low. to avoid accidental conten- tion when /hcs/hc1 is pulled low, it is advisable that the com decode register is written first prior to when the system configuration register is initialized. z189 miscellaneous control and interface registers (continued) figure 116. data bus direction (z180 bus master)
93 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z189 miscellaneous control and interface registers (continued) i/o write to on-chip peripherals i/o read from on-chip peripherals i/o write to off-chip peripherals write to memory write from memory refresh z80189 idle mode i/o and memory transactions z80189 data bus (ddout=0) z80189 data bus (ddout=1) in in out out z z z z in in z z z z i/o read from off-chip peripherals z z intack for on-chip peripheral intack for off-chip peripheral interrupt acknowledge transaction z80189 data bus (ddout=0) z80189 data bus (ddout=1) out out in in figure 117. data bus direction (z80180 is not bus master)
94 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ramcs/romcs to assist with decoding of rom and ram blocks of memory, three more registers and two pins have been added to the z80189. the two pins are /romcs and /ramcs. the three registers are the rombr, ramlbr and ramubr. ramubr, ramlbr ram upper boundary, ram lower range boundary range these two registers specify the address range for the /ramcs signal. when accessed memory addresses are less than or equal to the value programmed in the ramubr and greater than or equal to the value programmed in the ramlbr, /ramcs is asserted. in the case that these registers are programmed to overlap, /romcs takes pri- ority over /ramcs (/romcs is asserted and /ramcs is inactive). 11111111 a19-a12 ramlbr 7 65 4 321 0 figure 118. ramubr (z180 mpu address xxe6h) 11111111 a19-a12 ramubr 7 65 4 321 0 figure 119. ramlbr (z180 address xxe7h) figure 120. rombr (z180 address xxe8h) chip select signals are going active for the address range: romcs: (rombr) >= a19-a12 >= 0 /ramcs: (ramubr) >= a19-a12 >= (ramlbr) these registers are set to ffh at power-on reset, and the boundary addresses of rom and ram are as follows: rom lower boundary address (fixed) = 00000h rom upper boundary address (rombr register) = 0fffffh ram lower boundary address (ramlbr register) = 0fffffh ram upper boundary address (ramubr register) = 0fffffh since /romcs takes priority over /ramcs, the latter will never be asserted until the value in the rombr and ramlbr registers are re-initialized to lower values. rombr rom address boundary register this register specifies the address range for the /romcs signal. when accessed memory addresses are less than or equal to the value programmed in this register, the /romcs signal is asserted. this signal can be forced to a "1" (inactive state) by setting bit 3 in the system configuration register, to allow the user to overlay the ram area over the rom area. 11111111 a19-a12 rombr 7 65 4 321 0
95 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog z80189 rom/ram wait state generator a separate wait state generator is provided for access memory using /romcs and /ramcs. a single eight bit register is added to enable/disable this feature as well as provide two 3-bit fields that provides a 1-8 waits for each chip select. bit 7 /ramcs wait state generator enable. disable on power-up or reset. bit 6-4 /ramcs wait states 1-8. 8 wait states on power-up or reset. bit 3 /romcs wait state generator enable. disable on power-up or reset. bit 2-0 /romcs wait states 1-8. 8 wait states on power-up or reset. if wait state is disabled or ramcs and romcs is not asserted, the memory access is default to wait state programmed in the dcntl register of z180 dmas. note that the wait states inserted by this register and dcntl do not add. the actual number of wait states inserted is the greater of the two. note: that the wait states inserted by this register and dcntl do not add. the actual number of wait states inserted is the greater of the two. 00 /romcs wait states 1 - 8 7 65 4 321 0 /romcs wait state generator enable /ramcs wait states 1 - 8 /ramcs wait state generator enable figure 121. wsg chip select register (z180 mpu read/write, address xxd8h)
96 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog interrupt edge/pin mux registers bits 7-6 control the interrupt capture logic for the external /int2 pin. when programmed as 0x, the /int2 pin per- forms as the normal level detecting interrupt pin. when programmed as 10, the negative edge detection is en- abled. any falling edge will latch an active low on the internal /int2 of the z180. this interrupt must be cleared by writing a 1 to bit 7 of the port c data register. program- ming these control bits to 11 will enable rising edge interrupts to be latched. the latch is cleared in the same fashion as the falling edge. interrupt capture logic is not available in ev mode 1 (emulation adapter mode). bits 5-4 control the interrupt capture logic for the external /int1 pin. when programmed as 0x, the /int1 pin per- forms as the normal level detecting interrupt pin. when programmed as 10, the negative edge detection is en- abled. any falling edge will latch an active low on the internal /int1 of the z180. this interrupt must be cleared by writing a 1 to bit 6 of the port c data register. program- ming these control bits to 11 will enable rising edge interrupts to be latched. the latch is cleared in the same fashion as the falling edge. interrupt capture logic is not available in ev mode 1 (emulator adaption mode). bit 3 programming this bit to 1 selects the /mrd and the /mwr outputs. when this bit is set, /mreq will be removed for the qualification of both /ramcs and /romcs. by programming this bit to 0, the /mreq z180 and pc2 outputs are enabled. this bit is 0 upon reset. bit 2 selects the /iocs1 function which is the default for power up and /reset conditions. by programming this bit to 0, the ieo function is enabled for this multiplexed pin. bit 1 selects the low noise or normal drive feature for the z189 pins. the default at power up is normal drive for z189 pins. by programming this bit to 1, low noise for the z189 pins is chosen (not the z180 pins). programming this bit to 0 selects normal drive for the z189 pins. z189 pins include: all mimic output pins, rom/ram chip selects, bit i/o, iocs1, iocs2, and pc dma mailbox outputs. 00001100 halt recovery select 1 = 16 cycle delay on halt recovery 0 = no wait delay on halt recovery 7 65 4 321 0 low noise select 1 = select low noise for z189 (not z180) 0 = select normal drive for z189 pins ieo, /iocs1 select 1 = select /iocs1 function 0 = select ieo function /mreq, /hrd,pc2, /mwr select 1 select /mrd, /mwr 0 select /mreq, pc2 /int1 mode select 0x = normal level detect 10 = falling (neg) edge det 11 = rising (pos) edge det /int2 mode select 0x = normal level detect 10 = falling (neg) edge det 11 = rising (pos) edge det figure 122. interrupt edge/pin mux register (z180 mpu address xxdfh)
97 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog interrupt edge/pin mux registers (continued) bit 0 a 1 selects 16 cycle wait delay on recovery from halt if bit 5 of the z80189 enhancements register z180 mpu address d9h is set to zero. a 0 selects no wait delay on halt recovery. the definition of halt recovery is as follows. if this mode is selected the following pins assume the following states during halt and during the recovery, whether it is in halt, slp, idle or stby modes: address = z data bus = z /rd = z /wr = z /mreq = z /m1 = 1 st = 1 /iorq = 1 /busack = 1 (1) /rfsh = 1 (2) /iocs1 = z (3) /iocs2 = z hdrq0 = z (3) hdrq1 = z (3) note 1. this assumes that busreq is not activated during the halt. note 2. this assumes that the refresh is not enabled. this would not be a logical case since the address bus is tri-stated during the halt mode. note 3. this is only true if the function is enabled. the halt recovery mode is implemented by applying wait states to the next cpu operation following the exit from halt. all signals listed above are forced to their specified state (unless otherwise noted) during halt and also during the recovery state. sixteen cycles after the halt pin goes high the signals are released to their normal state. then eight wait states are inserted to allow proper access to accom- modate slow memories. z80189 enhancements register (z180 mpu address d9h) bit 7 forced /romcs memory boundary. when this bit is set to 1, it will force the /romcs boundary. a19 will be connected directly to /romcs. /romcs will then be asserted from 00000h-7ffffh. when this bit is cleared, /romcs will be accessed under the programmed ad- dress decoder range. this bit is 0 upon rest. note: in this mode, chip select assertion is not depen- dent on /mreq assertion. during sleep, /romcs will be forced inactive high. bit 6 forced /ramcs memory boundary. when this bit is set to 1, it will force the /ramcs boundary. /a19 will be connected to /ramcs. /ramcs will then be asserted from 8000h-fffffh. when this bit is cleared, /ramcs will be accessed under the programmed address decoder range. this bit is 0 upon reset. note: in this mode, chip select assertion is not depen- dent on /mreq assertion. during sleep, /ramcs is forced inactive. when using the forced memory boundaries, the memory access time requirement is improved. the improved memory access time equation is shown below: acc time < (2 + ws) *clkperiod-tad-tdrs note: when using forced rom boundary without forced ram boundary, or forced ram boundary without forced rom boundary, contention is possible (both /romcs & /ramcs active). care should be taken when program- ming memory boundaries such that there is no overlap. bit 5 force z180 halt mode (write/read). mpu signals are the same as z180 during halt modes. this allows bus acknowledge cycles during z189 halt modes. bit 1:4 reserved bit 0 phi output disable. when this bit is set, the phi output is not driven by the system clock. the phi output will be forced high in this mode. on production boards that do not use the phi output, this feature can be used to reduce emi. when this bit is reset, the system clock is output to phi pin. this bit is reset by default. this feature is not usable in ev mode 1 (emulation adapter) or ev mode 2 (emulation probe).
98 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog 0 00xxxx0 phi output disable 7 65 4 321 0 reserved force z180 halt mode forced /ramcs memory boundary forced /romcs memory boundary z80189 enhancements register i(z180 mpu address d9h) (continued) figure 123. z80189 enhancements register (z180 mpu address 09h) parallel ports registers 11111111 pa data direction register 0 = output 1 = input 7 65 4 321 0 figure 124. pa data direction register (z180 mpu address xxedh) the data direction register determines which are inputs and outputs in the pa data register. when a bit is set to a one, the corresponding bit in the pa data register is an input. if the bit is zero, then the corresponding bit is an output. the z80189 has three eight bit bidirectional ports. each bit is individually programmable for input or output. the ports consist of two registers: the port direction control register and the port data register. the port and direction register can be accessed in any page of i/o space since only the lowest eight address lines are decoded. bits pc7 and pc6 are input only bits and have the special function of reading the external value of the /int2 and /int1 pins. writing 1 to these bits will clear the edge detect interrupt logic when operating /int2 and/or /int1 in edge detect mode. when port b and port c bits 5-0 are deselected in the system configuration register, the data and data direc- tion registers are still available as read/write scratch registers. if a port is deselected and if the ddr bit is a 0, then the written value to that bit will be latched; and this value can be read back. if a port is deselected and if the ddr bit is a 1, then you could read only the external pin value; any write to that bit is latched but can be read back only with ddr=0.
99 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog parallel ports registers (continued) xxxxxxxx pa data register 7 65 4 321 0 11111111 pb data direction register 0 = output 1 = input 7 65 4 321 0 figure 126. pb data direction register (z180 mpu address xxe4h) the data direction register determines which are inputs and outputs in the pb data register. when a bit is set to a one, the corresponding bit in the pb data register is an input. if the bit is zero, then the corresponding bit is an output. figure 125. pa data register (z180 mpu address xxeeh) when the z180 mpu writes to the pa data register, the data is stored in the internal buffer. any bits that are output are then sent on to the output buffers. when the z180 mpu reads the pa data register, the data on the external pins is returned. xx111111 reserved 7 65 4 321 0 pb data direction register 0 = output 1 = input xxxxxxxx pb data register 7 65 4 321 0 figure 127. pb data register (z180 mpu address xxe5h) when the z180 mpu writes to the pb data register, the data is stored in the internal buffer. any bits that are output are then sent on to the output buffers. when the z180 mpu reads the pb data register, the data on the external pins is returned. figure 128. pc data direction register (z180 mpu address xxddh) the data direction register determines which are inputs and outputs in the pb data register. when a bit is set to a one, the corresponding bit in the pb data register is an input. if the bit is zero, then the corresponding bit is an output. xxxxxxxx pc data register 7 65 4 321 0 /int2, /int1 read ext data write b7=1 clears /int2 edge write b6=1 clears /int1 edge figure 129. pc, port c, data register (z180 mpu address xxdeh) when the z180 mpu writes to the pc data register, the data is stored in the internal buffer. any bits that are output are then sent on to the output buffers. when the z180 mpu reads the pc data register, the data on the external pins is returned. bits 7 and 6 serve the special function of reading the value of the external /int2 and /int1 lines. when operating either /int2 or /int1 in edge detection mode, the edge detect latch is reset by writing a '1' to bit 7 or 6 respectively. writing a '0' has no effect. these latches should be reset at the end of an /int1 or /int2 interrupts service routine when using edge-triggered interrupt routine.
100 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog emulation modes z80189 provides four modes of operation. the modes are selected by the ev1 and ev2 pins. these four modes allow for system development while the mimic is disabled, and t out is active. ev2 ev1 mode 0 0 0 normal mode, on-chip z180 bus master mode 1 0 1 emulation adapter mode mode 2 1 0 emulator probe mode mode 3 1 1 reserved mode 0 description mode 0 normal mode this is the normal operating mode for the z80189. mode 1 description the emulation adapter mode enables system develop- ment for the z189 with a readily available z180 emulator. the emulator provides the z180 mpu and z180 peripheral functions to the target system, with their signals passing through the emulation adapter. in emulation adapter mode, the z189s, z180 mpu and z180 peripheral signals are tri- stated or physically disconnected. the z189 continues to provide its brg, com port decoder, mimic and port functions and signals to the target system. the mode 1 effects on the z189 are: mode 0 mode 1 signal normal emulation adapter phi output input /m1 output input /mreq,/mrd output input /mwr output input /iorq output input /rd output input /wr output input /rfsh output input /halt output input st output input /busack output input /wait input output a19,a18 output input a17-a0 output input d7-d0 input/output input/output txa0 output tri-state /rts0 output tri-state txa1 output tri-state /int0 input output, open-drain mode 2 description in the emulator probe mode, all the z189 output signals are tri-stated. this scheme allows a z189 emulator probe to grab onto the z189 package leads on the target system. mode 3 description reserved for test mode. note also that in mode 1 and 3, the emulator must provide /mreq on the (/mreq) z80189 pin.
101 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog sleep, halt effect on mimic and z189 signals the following z80189 signals are driven high when z180 mpu enters a sleep or halt state: /romcs, /ramcs always high in sleep or halt. the following signals are high-z during sleep and halt: /iocs1 when so selected in the interrupt edge/pin mux register. /rd and /wr. a0-a19 is always high-z in power down. d0-d7 always high-z in power down modes. hdrq0, hdrq1 are high-z in halt or sleep. clock generator the z80189 zip ? uses the z189 mpus on-chip clock generator to supply system clock. the required clock is easily generated by connecting crystal to the external terminals (xtal, extal). recommended characteristics of the crystal and the val- ues for the capacitor are as follows (the values will change with crystal frequency). type of crystal: fundamental, parallel type crystal (at cut is recommended) frequency tolerance: application dependent cl, load capacitance: c l = c 1 = c 2 approximately 22 pf (acceptable range is 20-30 pf) rs, equivalent resistance: 60 ohms c in = c out = 15~22 pf. xtal extal crystal inputs c1 c2 figure 130. circuit configuration for crystal
102 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog electrical characteristics this section describes pins in terms of classes of inputs and outputs. pin output/input classification class "0" output: full time/totem pole v ol 0.4v max at i ol =2.0 ma v oh 2.4v min at i oh =200 m a slew rate 0.33 v/ns min at cload=50 pf c out =15 pf max (output or i/o) class "3" output: as "0" except tri-state class "s" output: open source capability active high, inactive tri-state class "t" output: tri-state v ol 0.4v max at i ol =16 ma v oh 2.4v min at i oh =16 ma output impedance 45 ohms max slew rate 0.05-0.40 v/ns (cload not state by ieee) c out =15 pf max (output or i/o) class "i" input: v il 0.8v max at v dd ~ = 5v v il 0.6v max at v dd ~ = 3.3v v ih 2.0v min ii 10 m a max, vi=0 to 5v (includes leakage if i/o) c in =5 pf max (if input only, see output type if i/o) class "r" input: v il 0.6v max v ih v dd -0.6 min at v dd ~= 5v v ih v dd -0.3 min at v dd ~= 3.3v ii 10 m a max, vi=0 to 5v c in =5 pf max note: all pins except xtal,extal have "weak latch" drivers. these drivers force the pin to a known state (logic high or logic low) and prevent pins from becoming unde- fined. unused pins need not be pulled up or pulled down to prevent esd or power drain.
103 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog the following table shows the characteristics of each pin in terms of the previous classifications. a blank in the "input" or "output" column indicates the pin does not have that function. table 17. pin classification characteristics input output default secondary type type function function i3st i 3 a0-a19 i 3 d0-d7 i 3 pb0 txs i 3 pb1 /ctso i 3 pb2 /dcd0 i 3 pb3 txa0 i 3 pb4 rxa0 i 3 pb5 txa1 i 3 pb6 rxa1 i 3 pb7 rxs//cts1 i 3 /hdack0 cka0//dreq0 i 3 ha9 cka1//tend0 ts hintr1 t out i 3 hc2 cks i 3 ha5 /dreq1 i t hdrq0 /rts0 3 /ramcs 3 /romcs i ev1 i ev2 i t hd0 pa0 i t hd1 pa1 i t hd2 pa2 i t hd3 pa3 i t hd4 pa4 i t hd5 pa5 i t hd6 pa6 i t hd7 pa7 i 3 pc5 i 3 pc3 i 3 pc2 /mwr i 3 pc1 i 3 pc0 i 3 pc4
104 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog electrical characteristics (continued) input output default secondary type type function function i 3 ha8 3 /iocs1 ieo i 3 ha7 iei i 3 ha6 i haen ts hintr2 i /hrd /dcd0 i /hwr /cts0 3 /hddis txa0 i 3 ha0 i 3 ha1 rxa0 i 3 ha2 i 3 /hcs hc1 3 /halt i 3 ha3 /rfsh i 3 /iorq i 3 /mreq mrd i 3 /iocs2 e i 3 /m1 i 3 /wr i 3 /rd i 3 phi 3 xtal i extal i 3 ha4 /wait i t hdrq1 /busack i 3 /hdack1 /busreq r /reset r /nmi i 3 /into i 3 /int1 pc6 i 3 /int2 pc7
105 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog package information 100-lead qfp package diagram
106 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog package information (continued) 100-vqfp package diagram
107 preliminary z80189/Z8L189 g eneral -p urpose e mbedded c ontrollers ds971890301 zilog ordering information z80189 Z8L189 33 mhz 20 mhz z8018933fsc Z8L18920fsc z8018933asc Z8L18920asc please check availability before placing order. package f = plastic quad flatpack a = vqfp (very small qfp) temperature s=0 c to +70 c speeds 33 = 33 mhz 20 = 20 mhz environmental c= plastic standard example: z 80189 33 f s c is a z80189, 33 mhz, qfp, 0 c to +70 c, plastic standard flow environmental flow temperature package speed product number zilog prefix zilogs products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 telex 910-338-7621 fax 408 370-8056 internet: http://www.zilog.com ? 1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of mer- chantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document.

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